ARM: Check in the actual change from the last commit.
The last commit was somehow empty. This was what was supposed to go in it.
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@@ -115,31 +115,31 @@ format DataOp {
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}});
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0x9: decode USEIMM {
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// The mask field is the same as the RN index.
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0: PredImmOp::msr_cpsr_imm({{
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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rotated_imm, RN, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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1: PredOp::msr_cpsr_reg({{
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0: PredOp::msr_cpsr_reg({{
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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Rm, RN, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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1: PredImmOp::msr_cpsr_imm({{
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uint32_t newCpsr =
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cpsrWriteByInstr(Cpsr | CondCodes,
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rotated_imm, RN, false);
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Cpsr = ~CondCodesMask & newCpsr;
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CondCodes = CondCodesMask & newCpsr;
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}});
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}
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0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
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0xb: decode USEIMM {
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// The mask field is the same as the RN index.
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0: PredImmOp::msr_spsr_imm({{
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0: PredOp::msr_spsr_reg({{
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Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
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}});
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1: PredImmOp::msr_spsr_imm({{
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Spsr = spsrWriteByInstr(Spsr, rotated_imm,
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RN, false);
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}});
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1: PredOp::msr_spsr_reg({{
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Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
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}});
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}
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}
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0x1: decode OPCODE {
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