Support for classic prefetchers in Ruby (#502)

This patch adds supports for using the "classic" prefetchers with ruby
cache controllers.

This pull request includes a few commits making the changes in this
order:
- Refactor decouples the classic cache and prefetchers interfaces
- Extras probes for later integration with ruby
- General ruby-side support
- Adds support for the CHI protocol

Commit [mem-ruby: support prefetcher in CHI
protocol](2bdb65653b)
may be used as example on how to add support for other protocols.

JIRA issues that may be related to this pull request:
    https://gem5.atlassian.net/browse/GEM5-457
    https://gem5.atlassian.net/browse/GEM5-1112

configs/common/cores/arm/O3_ARM_v7a.py

@@ -207,9 +207,8 @@ class O3_ARM_v7aL2(Cache):
     size = "1MB"
     assoc = 16
     write_buffers = 8
-    prefetch_on_access = True
     clusivity = "mostly_excl"
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=8, latency=1)
+    prefetcher = StridePrefetcher(degree=8, latency=1, prefetch_on_access=True)
     tags = BaseSetAssoc()
     replacement_policy = RandomRP()

configs/common/cores/arm/ex5_LITTLE.py

@@ -147,9 +147,8 @@ class L2(Cache):
     size = "512kB"
     assoc = 8
     write_buffers = 16
-    prefetch_on_access = True
     clusivity = "mostly_excl"
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=1, latency=1)
+    prefetcher = StridePrefetcher(degree=1, latency=1, prefetch_on_access=True)
     tags = BaseSetAssoc()
     replacement_policy = RandomRP()

configs/common/cores/arm/ex5_big.py

@@ -200,9 +200,8 @@ class L2(Cache):
     size = "2MB"
     assoc = 16
     write_buffers = 8
-    prefetch_on_access = True
     clusivity = "mostly_excl"
     # Simple stride prefetcher
-    prefetcher = StridePrefetcher(degree=8, latency=1)
+    prefetcher = StridePrefetcher(degree=8, latency=1, prefetch_on_access=True)
     tags = BaseSetAssoc()
     replacement_policy = RandomRP()

configs/ruby/CHI_config.py

@@ -1,4 +1,4 @@
-# Copyright (c) 2021,2022 ARM Limited
+# Copyright (c) 2021-2023 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -232,7 +232,8 @@ class CHI_L1Controller(CHI_Cache_Controller):
         super().__init__(ruby_system)
         self.sequencer = sequencer
         self.cache = cache
-        self.use_prefetcher = False
+        self.prefetcher = prefetcher
+        self.use_prefetcher = prefetcher != NULL
         self.send_evictions = True
         self.is_HN = False
         self.enable_DMT = False
@@ -269,7 +270,8 @@ class CHI_L2Controller(CHI_Cache_Controller):
         super().__init__(ruby_system)
         self.sequencer = NULL
         self.cache = cache
-        self.use_prefetcher = False
+        self.prefetcher = prefetcher
+        self.use_prefetcher = prefetcher != NULL
         self.allow_SD = True
         self.is_HN = False
         self.enable_DMT = False
@@ -305,7 +307,8 @@ class CHI_HNFController(CHI_Cache_Controller):
         super().__init__(ruby_system)
         self.sequencer = NULL
         self.cache = cache
-        self.use_prefetcher = False
+        self.prefetcher = prefetcher
+        self.use_prefetcher = prefetcher != NULL
         self.addr_ranges = addr_ranges
         self.allow_SD = True
         self.is_HN = True
@@ -381,6 +384,7 @@ class CHI_DMAController(CHI_Cache_Controller):
             size = "128"
             assoc = 1
 
+        self.prefetcher = NULL
         self.use_prefetcher = False
         self.cache = DummyCache()
         self.sequencer.dcache = NULL
@@ -500,11 +504,16 @@ class CHI_RNF(CHI_Node):
                 start_index_bit=self._block_size_bits, is_icache=False
             )
 
-            # Placeholders for future prefetcher support
-            if l1Iprefetcher_type != None or l1Dprefetcher_type != None:
-                m5.fatal("Prefetching not supported yet")
-            l1i_pf = NULL
-            l1d_pf = NULL
+            # prefetcher wrappers
+            if l1Iprefetcher_type != None:
+                l1i_pf = l1Iprefetcher_type()
+            else:
+                l1i_pf = NULL
+
+            if l1Dprefetcher_type != None:
+                l1d_pf = l1Dprefetcher_type()
+            else:
+                l1d_pf = NULL
 
             # cache controllers
             cpu.l1i = CHI_L1Controller(
@@ -549,9 +558,11 @@ class CHI_RNF(CHI_Node):
             l2_cache = cache_type(
                 start_index_bit=self._block_size_bits, is_icache=False
             )
+
             if pf_type != None:
-                m5.fatal("Prefetching not supported yet")
-            l2_pf = NULL
+                l2_pf = pf_type()
+            else:
+                l2_pf = NULL
 
             cpu.l2 = CHI_L2Controller(self._ruby_system, l2_cache, l2_pf)