becba00d95
Remove the prefetch_on_access and prefetch_on_pf_hit from BaseCache. BasePrefetch no longer expects this params to exist in the parent. Configurations that set these parameter using the cache object were fixed. Change-Id: I9ab6a545eaf930ee41ebda74e2b6b8bad0ca35a7 Signed-off-by: Tiago Mück <tiago.muck@arm.com>
155 lines
5.1 KiB
Python
155 lines
5.1 KiB
Python
# Copyright (c) 2012 The Regents of The University of Michigan
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# Copyright (c) 2016 Centre National de la Recherche Scientifique
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.objects import *
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# -----------------------------------------------------------------------
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# ex5 LITTLE core (based on the ARM Cortex-A7)
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# -----------------------------------------------------------------------
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# Simple ALU Instructions have a latency of 3
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class ex5_LITTLE_Simple_Int(MinorDefaultIntFU):
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opList = [OpDesc(opClass="IntAlu", opLat=4)]
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# Complex ALU instructions have a variable latencies
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class ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU):
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opList = [OpDesc(opClass="IntMult", opLat=7)]
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class ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU):
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opList = [OpDesc(opClass="IntDiv", opLat=9)]
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# Floating point and SIMD instructions
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class ex5_LITTLE_FP(MinorDefaultFloatSimdFU):
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opList = [
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OpDesc(opClass="SimdAdd", opLat=6),
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OpDesc(opClass="SimdAddAcc", opLat=4),
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OpDesc(opClass="SimdAlu", opLat=4),
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OpDesc(opClass="SimdCmp", opLat=1),
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OpDesc(opClass="SimdCvt", opLat=3),
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OpDesc(opClass="SimdMisc", opLat=3),
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OpDesc(opClass="SimdMult", opLat=4),
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OpDesc(opClass="SimdMultAcc", opLat=5),
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OpDesc(opClass="SimdMatMultAcc", opLat=5),
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OpDesc(opClass="SimdShift", opLat=3),
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OpDesc(opClass="SimdShiftAcc", opLat=3),
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OpDesc(opClass="SimdSqrt", opLat=9),
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OpDesc(opClass="SimdFloatAdd", opLat=8),
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OpDesc(opClass="SimdFloatAlu", opLat=6),
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OpDesc(opClass="SimdFloatCmp", opLat=6),
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OpDesc(opClass="SimdFloatCvt", opLat=6),
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OpDesc(opClass="SimdFloatDiv", opLat=20, pipelined=False),
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OpDesc(opClass="SimdFloatMisc", opLat=6),
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OpDesc(opClass="SimdFloatMult", opLat=15),
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OpDesc(opClass="SimdFloatMultAcc", opLat=6),
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OpDesc(opClass="SimdFloatMatMultAcc", opLat=6),
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OpDesc(opClass="SimdFloatSqrt", opLat=17),
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OpDesc(opClass="FloatAdd", opLat=8),
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OpDesc(opClass="FloatCmp", opLat=6),
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OpDesc(opClass="FloatCvt", opLat=6),
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OpDesc(opClass="FloatDiv", opLat=15, pipelined=False),
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OpDesc(opClass="FloatSqrt", opLat=33),
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OpDesc(opClass="FloatMult", opLat=6),
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]
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# Load/Store Units
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class ex5_LITTLE_MemFU(MinorDefaultMemFU):
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opList = [
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OpDesc(opClass="MemRead", opLat=1),
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OpDesc(opClass="MemWrite", opLat=1),
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]
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# Misc Unit
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class ex5_LITTLE_MiscFU(MinorDefaultMiscFU):
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opList = [
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OpDesc(opClass="IprAccess", opLat=1),
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OpDesc(opClass="InstPrefetch", opLat=1),
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]
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# Functional Units for this CPU
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class ex5_LITTLE_FUP(MinorFUPool):
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funcUnits = [
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ex5_LITTLE_Simple_Int(),
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ex5_LITTLE_Simple_Int(),
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ex5_LITTLE_Complex_IntMul(),
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ex5_LITTLE_Complex_IntDiv(),
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ex5_LITTLE_FP(),
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ex5_LITTLE_MemFU(),
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ex5_LITTLE_MiscFU(),
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]
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class ex5_LITTLE(ArmMinorCPU):
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executeFuncUnits = ex5_LITTLE_FUP()
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class L1Cache(Cache):
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tag_latency = 2
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data_latency = 2
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response_latency = 2
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tgts_per_mshr = 8
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# Consider the L2 a victim cache also for clean lines
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writeback_clean = True
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class L1I(L1Cache):
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mshrs = 2
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size = "32kB"
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assoc = 2
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is_read_only = True
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tgts_per_mshr = 20
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class L1D(L1Cache):
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mshrs = 4
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size = "32kB"
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assoc = 4
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write_buffers = 4
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# L2 Cache
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class L2(Cache):
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tag_latency = 9
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data_latency = 9
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response_latency = 9
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mshrs = 8
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tgts_per_mshr = 12
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size = "512kB"
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assoc = 8
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write_buffers = 16
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clusivity = "mostly_excl"
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# Simple stride prefetcher
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prefetcher = StridePrefetcher(degree=1, latency=1, prefetch_on_access=True)
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tags = BaseSetAssoc()
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replacement_policy = RandomRP()
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