arch-riscv: Fix fence.i instruction in O3 CPU (#816)

arch-riscv: Fix fence.i instruction in O3 CPU
2024-01-30 15:39:32 -08:00
parent d1fca18eb3 d94ef08a36
commit b3870ee7b0
1 changed files with 2 additions and 1 deletions
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -771,7 +771,8 @@ decode QUADRANT default Unknown::unknown() {
                0x0: fence({{
                }}, uint64_t, IsReadBarrier, IsWriteBarrier, No_OpClass);
                0x1: fence_i({{
-                }}, uint64_t, IsNonSpeculative, IsSerializeAfter, No_OpClass);
+                }}, uint64_t, IsNonSpeculative, IsSerializeAfter,
+                    IsSquashAfter, No_OpClass);
            }

            0x2: decode FUNCT12 {