X86: Make the segment register reading microops use merge.

src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py

@@ -142,7 +142,7 @@ processCSDescriptor:
     # Here, we know we're -not- in 64 bit mode, so we should do the
     # appropriate/other RIP checks.
     # if temp_RIP > CS.limit throw #GP(0)
-    rdlimit t6, cs
+    rdlimit t6, cs, dataSize=8
     subi t0, t1, t6, flags=(ECF,)
     fault "new GeneralProtection(0)", flags=(CECF,)
 

src/arch/x86/isa/microops/regop.isa

@@ -1052,22 +1052,22 @@ let {{
 
     class Rdbase(SegOp):
         code = '''
-            DestReg = SegBaseSrc1;
+            DestReg = merge(DestReg, SegBaseSrc1, dataSize);
         '''
 
     class Rdlimit(SegOp):
         code = '''
-            DestReg = SegLimitSrc1;
+            DestReg = merge(DestReg, SegLimitSrc1, dataSize);
         '''
 
     class RdAttr(SegOp):
         code = '''
-            DestReg = SegAttrSrc1;
+            DestReg = merge(DestReg, SegAttrSrc1, dataSize);
         '''
 
     class Rdsel(SegOp):
         code = '''
-            DestReg = SegSelSrc1;
+            DestReg = merge(DestReg, SegSelSrc1, dataSize);
         '''
 
     class Rdval(RegOp):