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x86: Flag instructions that call suspend as IsQuiesce

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The o3 cpu relies upon instructions that suspend a thread context being
flagged as "IsQuiesce".  If they are not, unpredictable behavior can occur.
This patch fixes that for the x86 ISA.
This commit is contained in:
Mitch Hayenga
2014-09-03 07:42:46 -04:00
parent 659bdc1a6b
commit afbae1ec95
2 changed files with 5 additions and 4 deletions
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6
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View File

@@ -141,13 +141,13 @@
}}, IsNonSpeculative);
0x01: m5quiesce({{
PseudoInst::quiesce(xc->tcBase());
}}, IsNonSpeculative);
}}, IsNonSpeculative, IsQuiesce);
0x02: m5quiesceNs({{
PseudoInst::quiesceNs(xc->tcBase(), Rdi);
}}, IsNonSpeculative);
}}, IsNonSpeculative, IsQuiesce);
0x03: m5quiesceCycle({{
PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
}}, IsNonSpeculative);
}}, IsNonSpeculative, IsQuiesce);
0x04: m5quiesceTime({{
Rax = PseudoInst::quiesceTime(xc->tcBase());
}}, IsNonSpeculative);

3
src/arch/x86/isa/microops/specop.isa
View File

@@ -63,7 +63,8 @@ output header {{
MicroHalt(ExtMachInst _machInst, const char * instMnem,
uint64_t setFlags) :
X86MicroopBase(_machInst, "halt", instMnem,
setFlags | (ULL(1) << StaticInst::IsNonSpeculative),
setFlags | (ULL(1) << StaticInst::IsNonSpeculative) |
(ULL(1) << StaticInst::IsQuiesce),
No_OpClass)
{
}