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CPU/Cache: Fix some errors exposed by valgrind

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This commit is contained in:
Ali Saidi
2010-09-30 09:35:19 -05:00
parent c41e633e0e
commit aef4a9904e
2 changed files with 6 additions and 5 deletions
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8
src/cpu/simple/timing.cc
View File

@@ -274,7 +274,7 @@ TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
{
PacketPtr pkt;
buildPacket(pkt, req, read);
pkt->dataDynamic<uint8_t>(data);
pkt->dataDynamicArray<uint8_t>(data);
if (req->getFlags().isSet(Request::NO_ACCESS)) {
assert(!dcache_pkt);
pkt->makeResponse();
@@ -402,7 +402,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
Packet::Broadcast);
pkt->dataDynamic<uint8_t>(data);
pkt->dataDynamicArray<uint8_t>(data);
pkt1->dataStatic<uint8_t>(data);
pkt2->dataStatic<uint8_t>(data + req1->getSize());
@@ -602,7 +602,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
if (traceData) {
traceData->setData(data);
}
T *dataP = new T;
T *dataP = (T*) new uint8_t[sizeof(T)];
*dataP = TheISA::htog(data);
return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
@@ -674,7 +674,7 @@ TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
if (state->isPrefetch()) {
state->setNoFault();
}
delete state->data;
delete [] state->data;
state->deleteReqs();
translationFault(state->getFault());
} else {

3
src/mem/packet.hh
View File

@@ -705,7 +705,8 @@ class Packet : public FastAlloc, public Printable
void
setData(uint8_t *p)
{
std::memcpy(getPtr<uint8_t>(), p, getSize());
if (p != getPtr<uint8_t>())
std::memcpy(getPtr<uint8_t>(), p, getSize());
}
/**