arch-arm: Generalize SCTLR_RST behaviour

This is supposed to be employed as a reset value for SCTLR.
Rather than implementing this misc reg specific feature, we
provide a more general logic for changing the reset value
of any register.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ib61019ec499b35382289fe18740c90eee5de4907
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70459
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

src/arch/arm/isa.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2022 Arm Limited
+ * Copyright (c) 2010-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -91,8 +91,6 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
     _regClasses.push_back(&ccRegClass);
     _regClasses.push_back(&miscRegClass);
 
-    miscRegs[MISCREG_SCTLR_RST] = 0;
-
     // Hook up a dummy device if we haven't been configured with a
     // real PMU. By using a dummy device, we don't need to check that
     // the PMU exist every time we try to access a PMU register.
@@ -140,7 +138,6 @@ ISA::clear()
         getMMUPtr(tc)->invalidateMiscReg();
     }
 
-    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
     for (auto idx = 0; idx < NUM_MISCREGS; idx++) {
         miscRegs[idx] = lookUpMiscReg[idx].reset();
     }
@@ -221,11 +218,11 @@ ISA::clear()
     }
 
     // Initialize AArch32 state...
-    clear32(p, sctlr_rst);
+    clear32(p);
 }
 
 void
-ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
+ISA::clear32(const ArmISAParams &p)
 {
     CPSR cpsr = 0;
     cpsr.mode = MODE_USER;
@@ -238,9 +235,6 @@ ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
     updateRegMap(cpsr);
 
     SCTLR sctlr = 0;
-    sctlr.te = (bool) sctlr_rst.te;
-    sctlr.nmfi = (bool) sctlr_rst.nmfi;
-    sctlr.v = (bool) sctlr_rst.v;
     sctlr.u = 1;
     sctlr.xp = 1;
     sctlr.rao2 = 1;
@@ -249,7 +243,6 @@ ISA::clear32(const ArmISAParams &p, const SCTLR &sctlr_rst)
     sctlr.uci = 1;
     sctlr.dze = 1;
     miscRegs[MISCREG_SCTLR_NS] = sctlr;
-    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
     miscRegs[MISCREG_HCPTR] = 0;
 
     miscRegs[MISCREG_CPACR] = 0;
@@ -2084,6 +2077,20 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
     }
 }
 
+RegVal
+ISA::readMiscRegReset(RegIndex idx) const
+{
+    int flat_idx = flattenMiscIndex(idx);
+    return lookUpMiscReg[flat_idx].reset();
+}
+
+void
+ISA::setMiscRegReset(RegIndex idx, RegVal val)
+{
+    int flat_idx = flattenMiscIndex(idx);
+    InitReg(flat_idx).reset(val);
+}
+
 BaseISADevice &
 ISA::getGenericTimer()
 {

src/arch/arm/isa.hh

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2022 ARM Limited
+ * Copyright (c) 2010, 2012-2023 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -170,7 +170,7 @@ namespace ArmISA
         void clear() override;
 
       protected:
-        void clear32(const ArmISAParams &p, const SCTLR &sctlr_rst);
+        void clear32(const ArmISAParams &p);
         void clear64(const ArmISAParams &p);
         void initID32(const ArmISAParams &p);
         void initID64(const ArmISAParams &p);
@@ -201,6 +201,9 @@ namespace ArmISA
         void setMiscRegNoEffect(RegIndex idx, RegVal val) override;
         void setMiscReg(RegIndex, RegVal val) override;
 
+        RegVal readMiscRegReset(RegIndex) const;
+        void setMiscRegReset(RegIndex, RegVal val);
+
         int
         flattenMiscIndex(int reg) const
         {

src/arch/arm/regs/misc.cc

@@ -2196,8 +2196,6 @@ ISA::initializeMiscRegMetadata()
       .bankedChild();
     InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
       .mutex();
-    InitReg(MISCREG_SCTLR_RST)
-      .allPrivileges();
     InitReg(MISCREG_SEV_MAILBOX)
       .allPrivileges();
     InitReg(MISCREG_TLBINEEDSYNC)

src/arch/arm/regs/misc.hh

@@ -93,7 +93,6 @@ namespace ArmISA
         MISCREG_NMRR_MAIR1_NS,
         MISCREG_NMRR_MAIR1_S,
         MISCREG_PMXEVTYPER_PMCCFILTR,
-        MISCREG_SCTLR_RST,
         MISCREG_SEV_MAILBOX,
         MISCREG_TLBINEEDSYNC,
 
@@ -1752,7 +1751,6 @@ namespace ArmISA
         "nmrr_mair1_ns",
         "nmrr_mair1_s",
         "pmxevtyper_pmccfiltr",
-        "sctlr_rst",
         "sev_mailbox",
         "tlbi_needsync",