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mem-ruby: fix SimpleNetwork WeightBased routing

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Individual link weights are propagated to the routing algorithms and
WeightBased routing now uses this information to select the output
link when multiple routing options exist.

JIRA: https://gem5.atlassian.net/browse/GEM5-920

Change-Id: I86a4deb610a1b94abf745e9ef249961fb52e9800
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41860
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Tiago Mück
2020-08-13 20:37:39 -05:00
committed by Tiago Muck
parent f748fbe7e1
commit ac278e44f9
8 changed files with 34 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mem/ruby/network/simple/PerfectSwitch.cc
View File

@@ -95,13 +95,15 @@ PerfectSwitch::addInPort(const std::vector<MessageBuffer*>& in)
void
PerfectSwitch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
const PortDirection &dst_inport)
const PortDirection &dst_inport,
int link_weight)
{
// Add to routing unit
m_switch->getRoutingUnit().addOutPort(m_out.size(),
out,
routing_table_entry,
dst_inport);
dst_inport,
link_weight);
m_out.push_back(out);
}

3
src/mem/ruby/network/simple/PerfectSwitch.hh
View File

@@ -79,7 +79,8 @@ class PerfectSwitch : public Consumer
void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
const PortDirection &dst_inport);
const PortDirection &dst_inport,
int link_weight);
int getInLinks() const { return m_in.size(); }
int getOutLinks() const { return m_out.size(); }

4
src/mem/ruby/network/simple/SimpleNetwork.cc
View File

@@ -120,7 +120,8 @@ SimpleNetwork::makeExtOutLink(SwitchID src, NodeID global_dest,
m_fromNetQueues[local_dest].resize(num_vnets, nullptr);
m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
routing_table_entry[0], simple_link->m_latency,
routing_table_entry[0],
simple_link->m_latency, 0,
simple_link->m_bw_multiplier);
}
@@ -147,6 +148,7 @@ SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link,
m_switches[dest]->addInPort(simple_link->m_buffers);
m_switches[src]->addOutPort(simple_link->m_buffers, routing_table_entry[0],
simple_link->m_latency,
simple_link->m_weight,
simple_link->m_bw_multiplier,
dst_inport);
// Maitain a global list of buffers (used for functional accesses only)

5
src/mem/ruby/network/simple/Switch.cc
View File

@@ -85,7 +85,8 @@ Switch::addInPort(const std::vector<MessageBuffer*>& in)
void
Switch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
Cycles link_latency, int bw_multiplier,
Cycles link_latency, int link_weight,
int bw_multiplier,
PortDirection dst_inport)
{
const std::vector<int> &physical_vnets_channels =
@@ -122,7 +123,7 @@ Switch::addOutPort(const std::vector<MessageBuffer*>& out,
// Hook the queues to the PerfectSwitch
perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
dst_inport);
dst_inport, link_weight);
// Hook the queues to the Throttle
throttles.back().addLinks(intermediateBuffers, out);

2
src/mem/ruby/network/simple/Switch.hh
View File

@@ -92,7 +92,7 @@ class Switch : public BasicRouter
void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
Cycles link_latency, int bw_multiplier,
Cycles link_latency, int link_weight, int bw_multiplier,
PortDirection dst_inport = "");
void resetStats();

3
src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
View File

@@ -69,7 +69,8 @@ class BaseRoutingUnit : public SimObject
virtual void addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
const PortDirection &direction) = 0;
const PortDirection &direction,
int link_weight) = 0;
struct RouteInfo
{

15
src/mem/ruby/network/simple/routing/WeightBased.cc
View File

@@ -60,13 +60,15 @@ void
WeightBased::addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
const PortDirection &direction)
const PortDirection &direction,
int link_weight)
{
gem5_assert(link_id == m_links.size());
m_links.emplace_back(new LinkInfo{link_id,
routing_table_entry,
m_out_buffer,
static_cast<int>(link_id)});
0, link_weight});
sortLinks();
}
void
@@ -81,7 +83,7 @@ WeightBased::route(const Message &msg,
// Don't adaptively route
// Makes sure ordering is reset
for (auto &link : m_links)
link->m_order = static_cast<int>(link->m_link_id);
link->m_order = 0;
} else {
// Find how clogged each link is
for (auto &link : m_links) {
@@ -96,12 +98,7 @@ WeightBased::route(const Message &msg,
(out_queue_length << 8) | random_mt.random(0, 0xff);
}
}
std::sort(m_links.begin(), m_links.end(),
[](const std::unique_ptr<LinkInfo> &a,
const std::unique_ptr<LinkInfo> &b) {
return a->m_order < b->m_order;
});
sortLinks();
}
findRoute(msg, out_links);

14
src/mem/ruby/network/simple/routing/WeightBased.hh
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@@ -60,7 +60,8 @@ class WeightBased : public BaseRoutingUnit
void addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
const PortDirection &direction) override;
const PortDirection &direction,
int link_weight) override;
void route(const Message &msg,
int vnet,
@@ -74,6 +75,7 @@ class WeightBased : public BaseRoutingUnit
const NetDest m_routing_entry;
const std::vector<MessageBuffer*> m_out_buffers;
int m_order;
int m_weight;
};
std::vector<std::unique_ptr<LinkInfo>> m_links;
@@ -81,6 +83,16 @@ class WeightBased : public BaseRoutingUnit
void findRoute(const Message &msg,
std::vector<RouteInfo> &out_links) const;
void sortLinks() {
std::sort(m_links.begin(), m_links.end(),
[](const auto &a, const auto &b) {
auto tup = [](const auto &li)
{ return std::make_tuple(li->m_order,
li->m_weight,
li->m_link_id);};
return tup(a) < tup(b);
});
}
};
} // namespace ruby