arch-riscv: Add enable_Zcd options to RiscvISA

The Zcd instructions overlap the Zcmp and Zcmt instruction

This option is used to enable/disable Zcd extension, implies enable
Zcmp/Zcmt extension. If Zcd is enable, the Zcmp and Zcmt is disabled.
Otherwise, Zcmp and Zcmt is enabled.

Spec: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc#zc-overview

Change-Id: I3788eb6539e13a210c9946efc43ca1fef4639560

src/arch/riscv/RiscvISA.py

@@ -114,6 +114,13 @@ class RiscvISA(BaseISA):
 
     enable_Zicbom_fs = Param.Bool(True, "Enable Zicbom extension in FS mode")
     enable_Zicboz_fs = Param.Bool(True, "Enable Zicboz extension in FS mode")
+    enable_Zcd = Param.Bool(
+        True,
+        "Enable Zcd extensions. "
+        "Set the option to false implies the Zcmp and Zcmt is enable as "
+        "c.fsdsp is overlap with them."
+        "Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc",
+    )
 
     wfi_resume_on_pending = Param.Bool(
         False,

src/arch/riscv/decoder.cc

@@ -44,6 +44,7 @@ Decoder::Decoder(const RiscvDecoderParams &p) : InstDecoder(p, &machInst)
     ISA *isa = dynamic_cast<ISA*>(p.isa);
     vlen = isa->getVecLenInBits();
     elen = isa->getVecElemLenInBits();
+    _enableZcd = isa->enableZcd();
     reset();
 }
 
@@ -127,6 +128,7 @@ Decoder::decode(PCStateBase &_next_pc)
     emi.vtype8  = next_pc.vtype() & 0xff;
     emi.vill    = next_pc.vtype().vill;
     emi.rv_type = static_cast<int>(next_pc.rvType());
+    emi.enable_zcd = _enableZcd;
 
     return decode(emi, next_pc.instAddr());
 }

src/arch/riscv/decoder.hh

@@ -62,6 +62,7 @@ class Decoder : public InstDecoder
 
     uint32_t vlen;
     uint32_t elen;
+    bool _enableZcd;
 
     virtual StaticInstPtr decodeInst(ExtMachInst mach_inst);
 

src/arch/riscv/isa.cc

@@ -260,7 +260,7 @@ RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
 ISA::ISA(const Params &p) : BaseISA(p, "riscv"),
     _rvType(p.riscv_type), enableRvv(p.enable_rvv), vlen(p.vlen), elen(p.elen),
     _privilegeModeSet(p.privilege_mode_set),
-    _wfiResumeOnPending(p.wfi_resume_on_pending)
+    _wfiResumeOnPending(p.wfi_resume_on_pending), _enableZcd(p.enable_Zcd)
 {
     _regClasses.push_back(&intRegClass);
     _regClasses.push_back(&floatRegClass);

src/arch/riscv/isa.hh

@@ -108,6 +108,14 @@ class ISA : public BaseISA
     */
     const bool _wfiResumeOnPending;
 
+    /**
+     * Enable Zcd extensions.
+     * Set the option to false implies the Zcmp and Zcmt is enable as c.fsdsp
+     * is overlap with them.
+     * Refs: https://github.com/riscv/riscv-isa-manual/blob/main/src/zc.adoc
+     */
+    bool _enableZcd;
+
   public:
     using Params = RiscvISAParams;
 
@@ -184,6 +192,8 @@ class ISA : public BaseISA
 
     bool resumeOnPending() { return _wfiResumeOnPending; }
 
+    bool enableZcd() { return _enableZcd; }
+
     virtual Addr getFaultHandlerAddr(
         RegIndex idx, uint64_t cause, bool intr) const;
 };

src/arch/riscv/isa/bitfields.isa

@@ -34,6 +34,7 @@
 // Bitfield definitions.
 //
 def bitfield RVTYPE rv_type;
+def bitfield ENABLE_ZCD enable_zcd;
 
 def bitfield QUADRANT <1:0>;
 def bitfield OPCODE5 <6:2>;

src/arch/riscv/isa/decoder.isa

@@ -54,6 +54,7 @@ decode QUADRANT default Unknown::unknown() {
             Rp2 = rvSext(sp + imm);
         }}, uint64_t);
         format CompressedLoad {
+            0x1: decode ENABLE_ZCD {
                 0x1: c_fld({{
                     offset = CIMM3 << 3 | CIMM2 << 6;
                 }}, {{
@@ -71,6 +72,7 @@ decode QUADRANT default Unknown::unknown() {
                 }}, {{
                     EA = rvSext(Rp1 + offset);
                 }});
+            }
             0x2: c_lw({{
                 offset = CIMM2<1:1> << 2 |
                          CIMM3 << 3 |
@@ -152,7 +154,8 @@ decode QUADRANT default Unknown::unknown() {
             }
         }
         format CompressedStore {
-            0x5: c_fsd({{
+            0x5: decode ENABLE_ZCD {
+                0x1: c_fsd({{
                     offset = CIMM3 << 3 | CIMM2 << 6;
                 }}, {{
                     STATUS status = xc->readMiscReg(MISCREG_STATUS);
@@ -164,6 +167,7 @@ decode QUADRANT default Unknown::unknown() {
                 }}, {{
                     EA = rvSext(Rp1 + offset);
                 }});
+            }
             0x6: c_sw({{
                 offset = CIMM2<1:1> << 2 |
                          CIMM3 << 3 |
@@ -381,6 +385,7 @@ decode QUADRANT default Unknown::unknown() {
             Rc1 = rvSext(Rc1 << imm);
         }}, uint64_t);
         format CompressedLoad {
+            0x1: decode ENABLE_ZCD {
                 0x1: c_fldsp({{
                     offset = CIMM5<4:3> << 3 |
                              CIMM1 << 5 |
@@ -398,6 +403,7 @@ decode QUADRANT default Unknown::unknown() {
                 }}, {{
                     EA = rvSext(sp + offset);
                 }});
+            }
             0x2: c_lwsp({{
                 offset = CIMM5<4:2> << 2 |
                          CIMM1 << 5 |
@@ -480,7 +486,8 @@ decode QUADRANT default Unknown::unknown() {
             }
         }
         format CompressedStore {
-            0x5: c_fsdsp({{
+            0x5: decode ENABLE_ZCD {
+                0x1: c_fsdsp({{
                     offset = CIMM6<5:3> << 3 |
                              CIMM6<2:0> << 6;
                 }}, {{
@@ -493,6 +500,7 @@ decode QUADRANT default Unknown::unknown() {
                 }}, {{
                     EA = rvSext(sp + offset);
                 }});
+            }
             0x6: c_swsp({{
                 offset = CIMM6<5:2> << 2 |
                          CIMM6<1:0> << 6;

src/arch/riscv/types.hh

@@ -58,6 +58,7 @@ BitUnion64(ExtMachInst)
     // Decoder state
     Bitfield<63, 62>    rv_type;
     Bitfield<61>        compressed;
+    Bitfield<60>        enable_zcd;
     // More bits for vector extension
     Bitfield<57, 41>    vl;     // [0, 2**16]
     Bitfield<40>        vill;