mem: Add a simple QoS-aware Memory Controller
This patch implements QoSMemorySink: a simple generic QoS-aware memory controller which inherits from QoS::MemCtrl. Change-Id: I537a4e2d4cb8f54fa0002eb088b2c6957afb9973 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11971 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Matthew Poremba <porembam@gmail.com>
This commit is contained in:
Matteo Andreozzi
committed by
Giacomo Travaglini
Giacomo Travaglini
parent
66f80b5a73
commit
aa103566d6
63
src/mem/qos/QoSMemSinkCtrl.py
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63
src/mem/qos/QoSMemSinkCtrl.py
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@@ -0,0 +1,63 @@
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# Copyright (c) 2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
|
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# modified or unmodified, in source code or in binary form.
|
||||
#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
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# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
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||||
#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Author: Matteo Andreozzi
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from m5.params import *
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from QoSMemCtrl import *
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class QoSMemSinkCtrl(QoSMemCtrl):
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type = 'QoSMemSinkCtrl'
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cxx_header = "mem/qos/mem_sink.hh"
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cxx_class = "QoS::MemSinkCtrl"
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port = SlavePort("Slave ports")
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# the basic configuration of the controller architecture, note
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# that each entry corresponds to a burst for the specific DRAM
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# configuration (e.g. x32 with burst length 8 is 32 bytes) and not
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# the cacheline size or request/packet size
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write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
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read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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# memory packet size
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memory_packet_size = Param.MemorySize("32B", "Memory packet size")
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# request latency - minimum timing between requests
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request_latency = Param.Latency("20ns", "Memory latency between requests")
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# response latency - time to issue a response once a request is serviced
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response_latency = Param.Latency("20ns", "Memory response latency")
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@@ -38,9 +38,11 @@
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Import('*')
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SimObject('QoSMemCtrl.py')
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SimObject('QoSMemSinkCtrl.py')
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SimObject('QoSPolicy.py')
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SimObject('QoSTurnaround.py')
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Source('policy.cc')
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Source('q_policy.cc')
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Source('mem_ctrl.cc')
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Source('mem_sink.cc')
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392
src/mem/qos/mem_sink.cc
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392
src/mem/qos/mem_sink.cc
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@@ -0,0 +1,392 @@
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/*
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* Copyright (c) 2018 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
|
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
|
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are
|
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* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Matteo Andreozzi
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*/
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#include "debug/Drain.hh"
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#include "debug/QOS.hh"
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#include "mem_sink.hh"
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#include "sim/system.hh"
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namespace QoS {
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MemSinkCtrl::MemSinkCtrl(const QoSMemSinkCtrlParams* p)
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: MemCtrl(p), requestLatency(p->request_latency),
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responseLatency(p->response_latency),
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memoryPacketSize(p->memory_packet_size),
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readBufferSize(p->read_buffer_size),
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writeBufferSize(p->write_buffer_size), port(name() + ".port", *this),
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retryRdReq(false), retryWrReq(false), nextRequest(0), nextReqEvent(this)
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{
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// Resize read and write queue to allocate space
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// for configured QoS priorities
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readQueue.resize(numPriorities());
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writeQueue.resize(numPriorities());
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}
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MemSinkCtrl::~MemSinkCtrl()
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{}
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void
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MemSinkCtrl::init()
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{
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MemCtrl::init();
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// Allow unconnected memories as this is used in several ruby
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// systems at the moment
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if (port.isConnected()) {
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port.sendRangeChange();
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}
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}
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bool
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MemSinkCtrl::readQueueFull(const uint64_t packets) const
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{
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return (totalReadQueueSize + packets > readBufferSize);
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}
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bool
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MemSinkCtrl::writeQueueFull(const uint64_t packets) const
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{
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return (totalWriteQueueSize + packets > writeBufferSize);
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}
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Tick
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MemSinkCtrl::recvAtomic(PacketPtr pkt)
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{
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panic_if(pkt->cacheResponding(),
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"%s Should not see packets where cache is responding\n",
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__func__);
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access(pkt);
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return responseLatency;
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}
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void
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MemSinkCtrl::recvFunctional(PacketPtr pkt)
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{
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pkt->pushLabel(name());
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functionalAccess(pkt);
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pkt->popLabel();
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}
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BaseSlavePort &
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MemSinkCtrl::getSlavePort(const std::string &interface, PortID idx)
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{
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if (interface != "port") {
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return MemObject::getSlavePort(interface, idx);
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} else {
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return port;
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}
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}
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bool
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MemSinkCtrl::recvTimingReq(PacketPtr pkt)
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{
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// Request accepted
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bool req_accepted = true;
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panic_if(!(pkt->isRead() || pkt->isWrite()),
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"%s. Should only see "
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"read and writes at memory controller\n",
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__func__);
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panic_if(pkt->cacheResponding(),
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"%s. Should not see packets where cache is responding\n",
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__func__);
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DPRINTF(QOS,
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"%s: MASTER %s request %s addr %lld size %d\n",
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__func__,
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_system->getMasterName(pkt->req->masterId()),
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pkt->cmdString(), pkt->getAddr(), pkt->getSize());
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uint64_t required_entries = divCeil(pkt->getSize(), memoryPacketSize);
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assert(required_entries);
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// Schedule packet
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uint8_t pkt_priority = qosSchedule({&readQueue, &writeQueue},
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memoryPacketSize, pkt);
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if (pkt->isRead()) {
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if (readQueueFull(required_entries)) {
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DPRINTF(QOS,
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"%s Read queue full, not accepting\n", __func__);
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// Remember that we have to retry this port
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retryRdReq = true;
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numReadRetries++;
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req_accepted = false;
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} else {
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// Enqueue the incoming packet into corresponding
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// QoS priority queue
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readQueue.at(pkt_priority).push_back(pkt);
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queuePolicy->enqueuePacket(pkt);
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}
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} else {
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if (writeQueueFull(required_entries)) {
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DPRINTF(QOS,
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"%s Write queue full, not accepting\n", __func__);
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// Remember that we have to retry this port
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retryWrReq = true;
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numWriteRetries++;
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req_accepted = false;
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} else {
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// Enqueue the incoming packet into corresponding QoS
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// priority queue
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writeQueue.at(pkt_priority).push_back(pkt);
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queuePolicy->enqueuePacket(pkt);
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}
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}
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if (req_accepted) {
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// The packet is accepted - log it
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logRequest(pkt->isRead()? READ : WRITE,
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pkt->req->masterId(),
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pkt->qosValue(),
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pkt->getAddr(),
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required_entries);
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}
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// Check if we have to process next request event
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if (!nextReqEvent.scheduled()) {
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DPRINTF(QOS,
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"%s scheduling next request at "
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"time %d (next is %d)\n", __func__,
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std::max(curTick(), nextRequest), nextRequest);
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schedule(nextReqEvent, std::max(curTick(), nextRequest));
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}
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return req_accepted;
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}
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void
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MemSinkCtrl::processNextReqEvent()
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{
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PacketPtr pkt = nullptr;
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// Evaluate bus direction
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busStateNext = selectNextBusState();
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// Record turnaround stats and update current state direction
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recordTurnaroundStats();
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// Set current bus state
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setCurrentBusState();
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// Access current direction buffer
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std::vector<PacketQueue>* queue_ptr = (busState == READ ? &readQueue :
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&writeQueue);
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DPRINTF(QOS,
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"%s DUMPING %s queues status\n", __func__,
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(busState == WRITE ? "WRITE" : "READ"));
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if (DTRACE(QOS)) {
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for (uint8_t i = 0; i < numPriorities(); ++i) {
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std::string plist = "";
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for (auto& e : (busState == WRITE ? writeQueue[i]: readQueue[i])) {
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plist += (std::to_string(e->req->masterId())) + " ";
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}
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DPRINTF(QOS,
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"%s priority Queue [%i] contains %i elements, "
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"packets are: [%s]\n", __func__, i,
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busState == WRITE ? writeQueueSizes[i] :
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readQueueSizes[i],
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plist);
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}
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}
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uint8_t curr_prio = numPriorities();
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for (auto queue = (*queue_ptr).rbegin();
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queue != (*queue_ptr).rend(); ++queue) {
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curr_prio--;
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DPRINTF(QOS,
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"%s checking %s queue [%d] priority [%d packets]\n",
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__func__, (busState == READ? "READ" : "WRITE"),
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curr_prio, queue->size());
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if (!queue->empty()) {
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// Call the queue policy to select packet from priority queue
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auto p_it = queuePolicy->selectPacket(&(*queue));
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pkt = *p_it;
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queue->erase(p_it);
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DPRINTF(QOS,
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"%s scheduling packet address %d for master %s from "
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"priority queue %d\n", __func__, pkt->getAddr(),
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_system->getMasterName(pkt->req->masterId()),
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curr_prio);
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break;
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}
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}
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assert(pkt);
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// Setup next request service time - do it here as retry request
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// hands over control to the port
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nextRequest = curTick() + requestLatency;
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uint64_t removed_entries = divCeil(pkt->getSize(), memoryPacketSize);
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DPRINTF(QOS,
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"%s scheduled packet address %d for master %s size is %d, "
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"corresponds to %d memory packets\n", __func__, pkt->getAddr(),
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_system->getMasterName(pkt->req->masterId()),
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pkt->getSize(), removed_entries);
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// Schedule response
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panic_if(!pkt->needsResponse(),
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"%s response not required\n", __func__);
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// Do the actual memory access which also turns the packet
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// into a response
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access(pkt);
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// Log the response
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logResponse(pkt->isRead()? READ : WRITE,
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pkt->req->masterId(),
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pkt->qosValue(),
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pkt->getAddr(),
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removed_entries, responseLatency);
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// Schedule the response
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port.schedTimingResp(pkt, curTick() + responseLatency, true);
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DPRINTF(QOS,
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"%s response scheduled at time %d\n",
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__func__, curTick() + responseLatency);
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// Finally - handle retry requests - this handles control
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// to the port, so do it last
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if (busState == READ && retryRdReq) {
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retryRdReq = false;
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port.sendRetryReq();
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} else if (busState == WRITE && retryWrReq) {
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retryWrReq = false;
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port.sendRetryReq();
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}
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// Check if we have to schedule another request event
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if ((totalReadQueueSize || totalWriteQueueSize) &&
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!nextReqEvent.scheduled()) {
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schedule(nextReqEvent, curTick() + requestLatency);
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DPRINTF(QOS,
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"%s scheduling next request event at tick %d\n",
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__func__, curTick() + requestLatency);
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}
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}
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DrainState
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MemSinkCtrl::drain()
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{
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if (totalReadQueueSize || totalWriteQueueSize) {
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DPRINTF(Drain,
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"%s queues have requests, waiting to drain\n",
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__func__);
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return DrainState::Draining;
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} else {
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return DrainState::Drained;
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}
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}
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void
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MemSinkCtrl::regStats()
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{
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MemCtrl::regStats();
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// Initialize all the stats
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using namespace Stats;
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numReadRetries.name(name() + ".numReadRetries")
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.desc("Number of read retries");
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numWriteRetries.name(name() + ".numWriteRetries")
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.desc("Number of write retries");
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}
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MemSinkCtrl::MemoryPort::MemoryPort(const std::string& n,
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MemSinkCtrl& m)
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: QueuedSlavePort(n, &m, queue), memory(m), queue(memory, *this)
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{}
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AddrRangeList
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MemSinkCtrl::MemoryPort::getAddrRanges() const
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{
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AddrRangeList ranges;
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ranges.push_back(memory.getAddrRange());
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return ranges;
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}
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Tick
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MemSinkCtrl::MemoryPort::recvAtomic(PacketPtr pkt)
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{
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return memory.recvAtomic(pkt);
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}
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void
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MemSinkCtrl::MemoryPort::recvFunctional(PacketPtr pkt)
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{
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pkt->pushLabel(memory.name());
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if (!queue.trySatisfyFunctional(pkt)) {
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// Default implementation of SimpleTimingPort::recvFunctional()
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// calls recvAtomic() and throws away the latency; we can save a
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// little here by just not calculating the latency.
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memory.recvFunctional(pkt);
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}
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pkt->popLabel();
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}
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bool
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MemSinkCtrl::MemoryPort::recvTimingReq(PacketPtr pkt)
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{
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return memory.recvTimingReq(pkt);
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}
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} // namespace QoS
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QoS::MemSinkCtrl*
|
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QoSMemSinkCtrlParams::create()
|
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{
|
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return new QoS::MemSinkCtrl(this);
|
||||
}
|
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|
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248
src/mem/qos/mem_sink.hh
Normal file
248
src/mem/qos/mem_sink.hh
Normal file
@@ -0,0 +1,248 @@
|
||||
/*
|
||||
* Copyright (c) 2018 ARM Limited
|
||||
* All rights reserved
|
||||
*
|
||||
* The license below extends only to copyright in the software and shall
|
||||
* not be construed as granting a license to any other intellectual
|
||||
* property including but not limited to intellectual property relating
|
||||
* to a hardware implementation of the functionality of the software
|
||||
* licensed hereunder. You may use the software subject to the license
|
||||
* terms below provided that you ensure that this notice is replicated
|
||||
* unmodified and in its entirety in all distributions of the software,
|
||||
* modified or unmodified, in source code or in binary form.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Author: Matteo Andreozzi
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __MEM_QOS_MEM_SINK_HH__
|
||||
#define __MEM_QOS_MEM_SINK_HH__
|
||||
|
||||
#include "mem/qos/mem_ctrl.hh"
|
||||
#include "mem/qport.hh"
|
||||
#include "params/QoSMemSinkCtrl.hh"
|
||||
|
||||
namespace QoS {
|
||||
|
||||
/**
|
||||
* QoS Memory Sink
|
||||
*
|
||||
* The QoS Memory Sink is a lightweight memory controller with QoS
|
||||
* support. It is meant to provide a QoS aware simple memory system
|
||||
* without the need of using a complex DRAM memory controller
|
||||
*/
|
||||
class MemSinkCtrl : public MemCtrl
|
||||
{
|
||||
protected:
|
||||
/**
|
||||
* The Request packets are store in a multiple dequeue structure,
|
||||
* based on their QoS priority
|
||||
*/
|
||||
using PacketQueue = std::deque<PacketPtr>;
|
||||
|
||||
private:
|
||||
class MemoryPort : public QueuedSlavePort
|
||||
{
|
||||
private:
|
||||
/** reference to parent memory object */
|
||||
MemSinkCtrl& memory;
|
||||
|
||||
/** Outgoing packet responses queue */
|
||||
RespPacketQueue queue;
|
||||
|
||||
public:
|
||||
/**
|
||||
* Constructor
|
||||
*
|
||||
* @param n port name
|
||||
* @param m reference to ProfileGen parent object
|
||||
*/
|
||||
MemoryPort(const std::string&, MemSinkCtrl&);
|
||||
|
||||
protected:
|
||||
/**
|
||||
* Receive a Packet in Atomic mode
|
||||
*
|
||||
* @param pkt pointer to memory packet
|
||||
* @return packet access latency in ticks
|
||||
*/
|
||||
Tick recvAtomic(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Receive a Packet in Functional mode
|
||||
*
|
||||
* @param pkt pointer to memory packet
|
||||
*/
|
||||
void recvFunctional(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Receive a Packet in Timing mode
|
||||
*
|
||||
* @param pkt pointer to memory packet
|
||||
* @return true if the request was accepted
|
||||
*/
|
||||
bool recvTimingReq(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Gets the configured address ranges for this port
|
||||
* @return the configured address ranges for this port
|
||||
*/
|
||||
AddrRangeList getAddrRanges() const;
|
||||
|
||||
};
|
||||
|
||||
public:
|
||||
/**
|
||||
* QoS Memory Sink Constructor
|
||||
*
|
||||
* @param p QoS Memory Sink configuration parameters
|
||||
*/
|
||||
MemSinkCtrl(const QoSMemSinkCtrlParams*);
|
||||
|
||||
virtual ~MemSinkCtrl();
|
||||
|
||||
/**
|
||||
* Checks and return the Drain state of this SimObject
|
||||
* @return current Drain state
|
||||
*/
|
||||
DrainState drain() override;
|
||||
|
||||
/**
|
||||
* Getter method to access this memory's slave port
|
||||
*
|
||||
* @param interface interface name
|
||||
* @param idx port ID number
|
||||
* @return reference to this memory's slave port
|
||||
*/
|
||||
BaseSlavePort& getSlavePort(const std::string&,
|
||||
PortID = InvalidPortID) override;
|
||||
|
||||
/**
|
||||
* Initializes this object
|
||||
*/
|
||||
void init() override;
|
||||
|
||||
protected:
|
||||
/** Memory between requests latency (ticks) */
|
||||
const Tick requestLatency;
|
||||
|
||||
/** Memory response latency (ticks) */
|
||||
const Tick responseLatency;
|
||||
|
||||
/** Memory packet size in bytes */
|
||||
const uint64_t memoryPacketSize;
|
||||
|
||||
/** Read request packets queue buffer size in #packets */
|
||||
const uint64_t readBufferSize;
|
||||
|
||||
/** Write request packets queue buffer size in #packets */
|
||||
const uint64_t writeBufferSize;
|
||||
|
||||
/** Memory slave port */
|
||||
MemoryPort port;
|
||||
|
||||
/** Read request pending */
|
||||
bool retryRdReq;
|
||||
|
||||
/** Write request pending */
|
||||
bool retryWrReq;
|
||||
|
||||
/** Next request service time */
|
||||
Tick nextRequest;
|
||||
|
||||
/** Count the number of read retries */
|
||||
Stats::Scalar numReadRetries;
|
||||
|
||||
/** Count the number of write retries */
|
||||
Stats::Scalar numWriteRetries;
|
||||
|
||||
/**
|
||||
* QoS-aware (per priority) incoming read requests packets queue
|
||||
*/
|
||||
std::vector<PacketQueue> readQueue;
|
||||
|
||||
/**
|
||||
* QoS-aware (per priority) incoming read requests packets queue
|
||||
*/
|
||||
std::vector<PacketQueue> writeQueue;
|
||||
|
||||
/**
|
||||
* Processes the next Request event according to configured
|
||||
* request latency
|
||||
*/
|
||||
void processNextReqEvent();
|
||||
|
||||
/** Event wrapper to schedule next request handler function */
|
||||
EventWrapper<
|
||||
MemSinkCtrl,
|
||||
&MemSinkCtrl::processNextReqEvent> nextReqEvent;
|
||||
|
||||
/**
|
||||
* Check if the read queue has room for more entries
|
||||
*
|
||||
* @param packets The number of entries needed in the read queue
|
||||
* @return true if read queue is full, false otherwise
|
||||
*/
|
||||
inline bool readQueueFull(const uint64_t packets) const;
|
||||
|
||||
/**
|
||||
* Check if the write queue has room for more entries
|
||||
*
|
||||
* @param packets The number of entries needed in the write queue
|
||||
* @return true if write queue is full, false otherwise
|
||||
*/
|
||||
inline bool writeQueueFull(const uint64_t packets) const;
|
||||
|
||||
/**
|
||||
* Receive a Packet in Atomic mode
|
||||
*
|
||||
* @param pkt pointer to memory packet
|
||||
* @return packet access latency in ticks
|
||||
*/
|
||||
Tick recvAtomic(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Receive a Packet in Functional mode
|
||||
*
|
||||
* @param pkt pointer to memory packet
|
||||
*/
|
||||
void recvFunctional(PacketPtr pkt);
|
||||
|
||||
/**
|
||||
* Receive a Packet in Timing mode
|
||||
*
|
||||
* @param pkt pointer to memory packet
|
||||
* @return true if the request was accepted
|
||||
*/
|
||||
bool recvTimingReq(PacketPtr pkt);
|
||||
|
||||
/** Registers statistics */
|
||||
void regStats() override;
|
||||
};
|
||||
|
||||
} // namespace QoS
|
||||
|
||||
#endif /* __MEM_QOS_MEM_SINK_HH__ */
|
||||
Reference in New Issue
Block a user