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arch-arm: Fix use of bitwise operators on booleans

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Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Javier Setoain
2019-03-14 17:42:44 +00:00
committed by Giacomo Travaglini
parent 93ad0d4324
commit a93fe3f3cf
1 changed files with 1 additions and 1 deletions
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2
src/arch/arm/isa/insts/sve.isa
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@@ -3182,9 +3182,9 @@ let {{
sveBinInst('bic', 'BicPred', 'SimdAluOp', unsignedTypes, bicCode,
PredType.MERGE, True)
# BIC (vectors, unpredicated)
bicCode = 'destElem = srcElem1 & ~srcElem2;'
sveBinInst('bic', 'BicUnpred', 'SimdAluOp', unsignedTypes, bicCode)
# BIC, BICS (predicates)
bicCode = 'destElem = srcElem1 && !srcElem2;'
svePredLogicalInst('bic', 'PredBic', 'SimdPredAluOp', ('uint8_t',),
bicCode)
svePredLogicalInst('bics', 'PredBics', 'SimdPredAluOp', ('uint8_t',),