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Basic MIPS floating point test works now ... I had to realize that when using the double FP reg the

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register with the higher # contains the most significant bytes...

arch/mips/isa/decoder.isa:
    divide instruction fixes
arch/mips/isa_traits.cc:
    use double as argument to cvt & round function.
    clean up cout statements in function.
arch/mips/isa_traits.hh:
    In MIPS the higher # reg of a doubles pair is ALSO the most significant reg.
    Once I switched this the basic MIPS FP test I had worked.

--HG--
extra : convert_revision : 45c80df229e6174d0b52fc7cfb530642b1f1fc35
This commit is contained in:
Korey Sewell
2006-05-07 13:26:15 -04:00
parent 34a5732bd3
commit a7565418d2
3 changed files with 15 additions and 24 deletions
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9
arch/mips/isa/decoder.isa
View File

@@ -149,13 +149,13 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x2: div({{
xc->setMiscReg(Hi,Rs.sw % Rt.sw);
xc->setMiscReg(Lo,Rs.sw / Rt.sw);
xc->setMiscReg(Hi,Rs.sd % Rt.sd);
xc->setMiscReg(Lo,Rs.sd / Rt.sd);
}});
0x3: divu({{
xc->setMiscReg(Hi,Rs.uw % Rt.uw);
xc->setMiscReg(Lo,Rs.uw / Rt.uw);
xc->setMiscReg(Hi,Rs.ud % Rt.ud);
xc->setMiscReg(Lo,Rs.ud / Rt.ud);
}});
}
}
@@ -435,6 +435,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x6: ctc1({{
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
uint32_t temp;
switch (FS)
{
case 25:

18
arch/mips/isa_traits.cc
View File

@@ -95,29 +95,19 @@ MipsISA::convert_and_round(uint64_t fp_val, ConvertType cvt_type, int rnd_mode)
uint64_t
MipsISA::convert_and_round(float fp_val, ConvertType cvt_type, int rnd_mode)
MipsISA::convert_and_round(double fp_val, ConvertType cvt_type, int rnd_mode)
{
void * ptr = &fp_val;
uint32_t fp_bits = * (uint32_t *) ptr;
cout << "Converting " << fp_val << " (" << hex << fp_bits << ") " << endl;
uint64_t ret_val = 0;
switch (cvt_type)
{
case SINGLE_TO_DOUBLE:
double double_val = fp_val;
void *double_ptr = &double_val;
uint64_t dp_bits = *(uint64_t *) double_ptr ;
cout << "To " << double_val << " (" << hex << dp_bits << ") " << endl;
double_ptr = &dp_bits;
cout << "Testing: " << *(double *) double_ptr << endl;
void *double_ptr = &double_val;
uint64_t dp_bits = *(uint64_t *) double_ptr ;
return dp_bits;
default:
panic("Invalid Floating Point Conversion Type (%d) being used.\n",cvt_type);
return ret_val;
return 0;
}
}

12
arch/mips/isa_traits.hh
View File

@@ -248,7 +248,7 @@ namespace MipsISA
return regs[floatReg];
case DoubleWidth:
return (FloatReg64)regs[floatReg] << 32 | regs[floatReg + 1];
return (FloatReg64)regs[floatReg + 1] << 32 | regs[floatReg];
default:
panic("Attempted to read a %d bit floating point register!", width);
@@ -269,8 +269,8 @@ namespace MipsISA
case DoubleWidth:
const void *double_ptr = &val;
FloatReg64 temp_double = *(FloatReg64 *) double_ptr;
regs[floatReg] = temp_double >> 32;
regs[floatReg + 1] = temp_double;
regs[floatReg + 1] = temp_double >> 32;
regs[floatReg] = temp_double;
break;
default:
@@ -291,8 +291,8 @@ namespace MipsISA
break;
case DoubleWidth:
regs[floatReg] = val >> 32;
regs[floatReg + 1] = val;
regs[floatReg + 1] = val >> 32;
regs[floatReg] = val;
break;
default:
@@ -336,7 +336,7 @@ namespace MipsISA
uint64_t convert_and_round(uint32_t fp_val,ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(uint64_t fp_val,ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(float fp_val,ConvertType cvt_type, int rnd_mode = 0);
uint64_t convert_and_round(double fp_val,ConvertType cvt_type, int rnd_mode = 0);
void copyRegs(ExecContext *src, ExecContext *dest);