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arch-arm: Simplify setting of isHyp for mem translations

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The isHyp descriptor is an old artifact of armv7 and it flags a PL2
(AArch32) or EL2 & EL2&0 (AArch64) translations.
It is commonly set according to the EL/mode [1] but it may differ from
the execution state in case of explicit translation requests (via
the AT instruction as an example [2]).

There is really no need to complicate the masking of isHyp. We should
just make use of the tranType method (in charge of setting aarch64EL)
to properly set aarch64EL, and make isHyp coincide with the case of
aarch64EL == EL2.

This is a step towards the removal of the isHyp flag.

More specifically the patch does the following:

* HypMode translation type moved in the EL2 case
The translation is used by

ATS1HR/ATS1HW:
Performs stage 1 address translation as defined for PL2 and the
Non-secure state

* S1S2NsTran translation type moved in the EL1 case
The translation is used by

ATS12NSOPR/ATS12NSOPW:
Performs stage 1 and 2 address translations as defined for PL1 and the
Non-secure state

* S1CTran translation type can be at either EL1 or EL3
The translation is used by

ATS1CPR/ATS1CPW
Performs stage 1 address translation as defined for PL1 and the current
Security state

[1]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/mmu.cc#L1281
[2]: https://github.com/gem5/gem5/blob/stable/src/arch/arm/mmu.cc#L1282

Change-Id: Ie653170f6053c5d8141a2de9f50febf5bf53ab9c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-12-28 09:21:45 +00:00
parent 2ff57b09d8
commit a6ca81906a
2 changed files with 14 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
src/arch/arm/mmu.cc
View File

@@ -1205,17 +1205,20 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
ArmTranslationType tran_type)
{
cpsr = tc->readMiscReg(MISCREG_CPSR);
hcr = tc->readMiscReg(MISCREG_HCR_EL2);
scr = tc->readMiscReg(MISCREG_SCR_EL3);
// Dependencies: SCR/SCR_EL3, CPSR
isSecure = ArmISA::isSecure(tc) &&
!(tran_type & HypMode) && !(tran_type & S1S2NsTran);
aarch64EL = tranTypeEL(cpsr, tran_type);
aarch64EL = tranTypeEL(cpsr, scr, tran_type);
aarch64 = isStage2 ?
ELIs64(tc, EL2) :
ELIs64(tc, aarch64EL == EL0 ? EL1 : aarch64EL);
hcr = tc->readMiscReg(MISCREG_HCR_EL2);
isHyp = aarch64EL == EL2;
if (aarch64) { // AArch64
// determine EL we need to translate in
switch (aarch64EL) {
@@ -1274,14 +1277,9 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
break;
}
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = aarch64EL != EL0;
if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = getVMID(tc);
isHyp = aarch64EL == EL2;
isHyp |= tran_type & HypMode;
isHyp &= (tran_type & S1S2NsTran) == 0;
isHyp &= (tran_type & S1CTran) == 0;
bool vm = hcr.vm;
if (HaveExt(tc, ArmExtension::FEAT_VHE) &&
hcr.e2h == 1 && hcr.tge ==1) {
@@ -1319,7 +1317,6 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
!isSecure));
ttbcr = tc->readMiscReg(snsBankedIndex(MISCREG_TTBCR, tc,
!isSecure));
scr = tc->readMiscReg(MISCREG_SCR_EL3);
isPriv = cpsr.mode != MODE_USER;
if (longDescFormatInUse(tc)) {
uint64_t ttbr_asid = tc->readMiscReg(
@@ -1338,14 +1335,9 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
!isSecure));
dacr = tc->readMiscReg(snsBankedIndex(MISCREG_DACR, tc,
!isSecure));
hcr = tc->readMiscReg(MISCREG_HCR_EL2);
if (mmu->release()->has(ArmExtension::VIRTUALIZATION)) {
vmid = bits(tc->readMiscReg(MISCREG_VTTBR), 55, 48);
isHyp = cpsr.mode == MODE_HYP;
isHyp |= tran_type & HypMode;
isHyp &= (tran_type & S1S2NsTran) == 0;
isHyp &= (tran_type & S1CTran) == 0;
if (isHyp) {
sctlr = tc->readMiscReg(MISCREG_HSCTLR);
}
@@ -1370,7 +1362,7 @@ MMU::CachedState::updateMiscReg(ThreadContext *tc,
}
ExceptionLevel
MMU::tranTypeEL(CPSR cpsr, ArmTranslationType type)
MMU::tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type)
{
switch (type) {
case S1E0Tran:
@@ -1379,18 +1371,21 @@ MMU::tranTypeEL(CPSR cpsr, ArmTranslationType type)
case S1E1Tran:
case S12E1Tran:
case S1S2NsTran:
return EL1;
case S1E2Tran:
case HypMode:
return EL2;
case S1E3Tran:
return EL3;
case NormalTran:
case S1CTran:
case S1S2NsTran:
case HypMode:
return currEL(cpsr) == EL3 && scr.ns == 0 ?
EL3 : EL1;
case NormalTran:
return currEL(cpsr);
default:

4
src/arch/arm/mmu.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2016, 2019-2022 Arm Limited
* Copyright (c) 2010-2013, 2016, 2019-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -388,7 +388,7 @@ class MMU : public BaseMMU
* a specific translation type. If the translation type doesn't
* specify an EL, we use the current EL.
*/
static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
static ExceptionLevel tranTypeEL(CPSR cpsr, SCR scr, ArmTranslationType type);
static bool hasUnprivRegime(ExceptionLevel el, bool e2h);