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arch-arm, dev-arm: Consistently use ISO prefixes

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We currently use the traditional SI-like prefixes to represent
binary multipliers in some contexts. This is ambiguous in many cases
since they overload the meaning of the SI prefix.

Here are some examples of commonly used in the industry:
  * Storage vendors define 1 MB as 10**6 bytes
  * Memory vendors define 1 MB as 2**20 bytes
  * Network equipment treats 1Mbit/s as 10**6 bits/s
  * Memory vendors define 1Mbit as 2**20 bits

In practice, this means that a FLASH chip on a storage bus uses
decimal prefixes, but that same flash chip on a memory bus uses binary
prefixes. It would also be reasonable to assume that the contents of a
1Mbit FLASH chip would take 0.1s to transfer over a 10Mbit Ethernet
link. That's however not the case due to different meanings of the
prefix.

The quantity 2MX is treated differently by gem5 depending on the unit
X:

  * Physical quantities (s, Hz, V, A, J, K, C, F) use decimal prefixes.
  * Interconnect and NoC bandwidths (B/s) use binary prefixes.
  * Network bandwidths (bps) use decimal prefixes.
  * Memory sizes and storage sizes (B) use binary prefixes.

Mitigate this ambiguity by consistently using the ISO/IEC/SI prefixes
for binary multipliers for parameters and comments where appropriate.

Change-Id: I9b47194d26d71c8ebedda6c31a5bac54b600d3bf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39575
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Andreas Sandberg
2021-01-21 09:47:16 +00:00
parent 61dbd95e1b
commit a6be3fd503
5 changed files with 49 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/arch/arm/ArmSemihosting.py
View File

@@ -53,10 +53,10 @@ class ArmSemihosting(SimObject):
files_root_dir = Param.String("",
"Host root directory for files handled by Semihosting")
mem_reserve = Param.MemorySize("32MB",
mem_reserve = Param.MemorySize("32MiB",
"Amount of memory to reserve at the start of the address map. This "
"memory won't be used by the heap reported to an application.");
stack_size = Param.MemorySize("32MB", "Application stack size");
stack_size = Param.MemorySize("32MiB", "Application stack size");
time = Param.Time('01/01/2009',
"System time to use ('Now' for actual time)")

24
src/arch/arm/table_walker.cc
View File

@@ -648,7 +648,7 @@ TableWalker::processWalkLPAE()
MISCREG_TTBR0, currState->tc, !currState->isSecure));
tsz = currState->ttbcr.t0sz;
currState->isUncacheable = currState->ttbcr.irgn0 == 0;
if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GB
if (ttbr0_max < (1ULL << 30)) // Upper limit < 1 GiB
start_lookup_level = L2;
} else if (currState->vaddr >= ttbr1_min) {
DPRINTF(TLB, " - Selecting TTBR1 (long-desc.)\n");
@@ -673,7 +673,7 @@ TableWalker::processWalkLPAE()
MISCREG_TTBR1, currState->tc, !currState->isSecure));
tsz = currState->ttbcr.t1sz;
currState->isUncacheable = currState->ttbcr.irgn1 == 0;
// Lower limit >= 3 GB
// Lower limit >= 3 GiB
if (ttbr1_min >= (1ULL << 31) + (1ULL << 30))
start_lookup_level = L2;
} else {
@@ -2379,16 +2379,16 @@ TableWalker::TableWalkerStats::TableWalkerStats(Stats::Group *parent)
pageSizes // see DDI 0487A D4-1661
.init(10)
.flags(Stats::total | Stats::pdf | Stats::dist | Stats::nozero);
pageSizes.subname(0, "4K");
pageSizes.subname(1, "16K");
pageSizes.subname(2, "64K");
pageSizes.subname(3, "1M");
pageSizes.subname(4, "2M");
pageSizes.subname(5, "16M");
pageSizes.subname(6, "32M");
pageSizes.subname(7, "512M");
pageSizes.subname(8, "1G");
pageSizes.subname(9, "4TB");
pageSizes.subname(0, "4KiB");
pageSizes.subname(1, "16KiB");
pageSizes.subname(2, "64KiB");
pageSizes.subname(3, "1MiB");
pageSizes.subname(4, "2MiB");
pageSizes.subname(5, "16MiB");
pageSizes.subname(6, "32MiB");
pageSizes.subname(7, "512MiB");
pageSizes.subname(8, "1GiB");
pageSizes.subname(9, "4TiB");
requestOrigin
.init(2,2) // Instruction/Data, requests/completed

18
src/arch/arm/table_walker.hh
View File

@@ -132,7 +132,7 @@ class TableWalker : public ClockedObject
return (EntryType)(data & 0x3);
}
/** Is the page a Supersection (16MB)?*/
/** Is the page a Supersection (16 MiB)?*/
bool supersection() const
{
return bits(data, 18);
@@ -434,8 +434,8 @@ class TableWalker : public ClockedObject
{
switch (bits(data, 1, 0)) {
case 0x1:
// In AArch64 blocks are not allowed at L0 for the 4 KB granule
// and at L1 for 16/64 KB granules
// In AArch64 blocks are not allowed at L0 for the
// 4 KiB granule and at L1 for 16/64 KiB granules
switch (grainSize) {
case Grain4KB:
if (lookupLevel == L0 || lookupLevel == L3)
@@ -451,7 +451,7 @@ class TableWalker : public ClockedObject
case Grain64KB:
// With Armv8.2-LPA (52bit PA) L1 Block descriptors
// are allowed for 64KB granule
// are allowed for 64KiB granule
if ((lookupLevel == L1 && physAddrRange == 52) ||
lookupLevel == L2)
return Block;
@@ -474,13 +474,13 @@ class TableWalker : public ClockedObject
if (type() == Block) {
switch (grainSize) {
case Grain4KB:
return lookupLevel == L1 ? 30 /* 1 GB */
: 21 /* 2 MB */;
return lookupLevel == L1 ? 30 /* 1 GiB */
: 21 /* 2 MiB */;
case Grain16KB:
return 25 /* 32 MB */;
return 25 /* 32 MiB */;
case Grain64KB:
return lookupLevel == L1 ? 42 /* 4TB MB */
: 29 /* 512 MB */;
return lookupLevel == L1 ? 42 /* 4 TiB */
: 29 /* 512 MiB */;
default:
panic("Invalid AArch64 VM granule size\n");
}

8
src/dev/arm/FlashDevice.py
View File

@@ -47,12 +47,12 @@ class DataDistribution(Enum): vals = ['sequential', 'stripe']
class FlashDevice(AbstractNVM):
type = 'FlashDevice'
cxx_header = "dev/arm/flash_device.hh"
# default blocksize is 128 kB.This seems to be the most common size in
# default blocksize is 128 KiB.This seems to be the most common size in
# mobile devices (not the image blocksize)
blk_size = Param.MemorySize("128kB", "Size of one disk block")
# disk page size is 2 kB. This is the most commonly used page size in
blk_size = Param.MemorySize("128KiB", "Size of one disk block")
# disk page size is 2 KiB. This is the most commonly used page size in
# flash devices
page_size = Param.MemorySize("2kB", "Size of one disk page")
page_size = Param.MemorySize("2KiB", "Size of one disk page")
# There are many GC flavors. It is impossible to cover them all; this
# parameter enables the approximation of different GC algorithms
GC_active = Param.Percent(50, "Percentage of the time (in whole numbers) \

44
src/dev/arm/RealView.py
View File

@@ -510,7 +510,7 @@ class HDLcd(AmbaDmaDevice):
frame_format = Param.ImageFormat("Auto",
"image format of the captured frame")
pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
pixel_buffer_size = Param.MemorySize32("2KiB", "Size of address range")
pxl_clk = Param.ClockDomain("Pixel clock source")
pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
@@ -645,7 +645,7 @@ class RealView(Platform):
type = 'RealView'
cxx_header = "dev/arm/realview.hh"
system = Param.System(Parent.any, "system")
_mem_regions = [ AddrRange(0, size='256MB') ]
_mem_regions = [ AddrRange(0, size='256MiB') ]
_num_pci_dev = 0
def _on_chip_devices(self):
@@ -742,15 +742,15 @@ class RealView(Platform):
state.addrCells(system.workload.cpu_release_addr)))
class VExpress_EMM(RealView):
_mem_regions = [ AddrRange('2GB', size='2GB') ]
_mem_regions = [ AddrRange('2GiB', size='2GiB') ]
# Ranges based on excluding what is part of on-chip I/O (gic,
# a9scu)
_off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
AddrRange(0x30000000, size='256MB'),
AddrRange(0x40000000, size='512MB'),
AddrRange(0x18000000, size='64MB'),
AddrRange(0x1C000000, size='64MB')]
_off_chip_ranges = [AddrRange(0x2F000000, size='16MiB'),
AddrRange(0x30000000, size='256MiB'),
AddrRange(0x40000000, size='512MiB'),
AddrRange(0x18000000, size='64MiB'),
AddrRange(0x1C000000, size='64MiB')]
# Platform control device (off-chip)
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
@@ -790,7 +790,7 @@ class VExpress_EMM(RealView):
### Off-chip devices ###
uart = Pl011(pio_addr=0x1c090000, interrupt=ArmSPI(num=37))
pci_host = GenericPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
conf_base=0x30000000, conf_size='256MiB', conf_device_bits=16,
pci_pio_base=0)
sys_counter = SystemCounter()
@@ -814,9 +814,9 @@ class VExpress_EMM(RealView):
cf_ctrl.BAR0 = PciLegacyIoBar(addr='0x1C1A0000', size='256B')
cf_ctrl.BAR1 = PciLegacyIoBar(addr='0x1C1A0100', size='4096B')
bootmem = SimpleMemory(range = AddrRange('64MB'),
bootmem = SimpleMemory(range = AddrRange('64MiB'),
conf_table_reported = False)
vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
vram = SimpleMemory(range = AddrRange(0x18000000, size='32MiB'),
conf_table_reported = False)
rtc = PL031(pio_addr=0x1C170000, interrupt=ArmSPI(num=36))
@@ -884,12 +884,12 @@ class VExpress_EMM(RealView):
cur_sys, boot_loader, 0x8000000, 0x80000000)
class VExpress_EMM64(VExpress_EMM):
# Three memory regions are specified totalling 512GB
_mem_regions = [ AddrRange('2GB', size='2GB'),
AddrRange('34GB', size='30GB'),
AddrRange('512GB', size='480GB') ]
# Three memory regions are specified totalling 512GiB
_mem_regions = [ AddrRange('2GiB', size='2GiB'),
AddrRange('34GiB', size='30GiB'),
AddrRange('512GiB', size='480GiB') ]
pci_host = GenericPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
conf_base=0x30000000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x2f000000)
def setupBootLoader(self, cur_sys, loc, boot_loader=None):
@@ -1038,7 +1038,7 @@ Interrupts:
"""
# Everything above 2GiB is memory
_mem_regions = [ AddrRange('2GB', size='510GB') ]
_mem_regions = [ AddrRange('2GiB', size='510GiB') ]
_off_chip_ranges = [
# CS1-CS5
@@ -1047,15 +1047,15 @@ Interrupts:
AddrRange(0x2f000000, 0x80000000),
]
bootmem = SimpleMemory(range=AddrRange(0, size='64MB'),
bootmem = SimpleMemory(range=AddrRange(0, size='64MiB'),
conf_table_reported=False)
# NOR flash, flash0
flash0 = SimpleMemory(range=AddrRange(0x08000000, size='64MB'),
flash0 = SimpleMemory(range=AddrRange(0x08000000, size='64MiB'),
conf_table_reported=False)
# Trusted SRAM
trusted_sram = SimpleMemory(range=AddrRange(0x04000000, size='256kB'),
trusted_sram = SimpleMemory(range=AddrRange(0x04000000, size='256KiB'),
conf_table_reported=False)
# Non-Trusted SRAM
@@ -1134,7 +1134,7 @@ Interrupts:
### gem5-specific off-chip devices ###
pci_host = GenericArmPciHost(
conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
conf_base=0x30000000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x2f000000,
pci_mem_base=0x40000000,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
@@ -1354,7 +1354,7 @@ class VExpress_GEM5_Foundation(VExpress_GEM5_Base):
its=NULL)
pci_host = GenericArmPciHost(
conf_base=0x40000000, conf_size='256MB', conf_device_bits=12,
conf_base=0x40000000, conf_size='256MiB', conf_device_bits=12,
pci_pio_base=0x50000000,
pci_mem_base=0x400000000,
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)