arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).

Change-Id: I32be58cce831c8c7d5b9e3d3f49f428a06c722a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49713
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/isa_parser/operand_list.py

@@ -116,12 +116,6 @@ class OperandList(object):
 
         self.numSrcRegs = len(srcs)
         self.numDestRegs = len(dests)
-        self.numFPDestRegs = sum(r.isFloatReg() for r in dests)
-        self.numIntDestRegs = sum(r.isIntReg() for r in dests)
-        self.numVecDestRegs = sum(r.isVecReg() for r in dests)
-        self.numVecPredDestRegs = sum(r.isVecPredReg() for r in dests)
-        self.numCCDestRegs = sum(r.isCCReg() for r in dests)
-        self.numMiscDestRegs = sum(r.isControlReg() for r in dests)
 
         if len(mem) > 1:
             error("Code block has more than one memory operand")

src/cpu/o3/dyn_inst.hh

@@ -680,21 +680,10 @@ class DynInst : public ExecContext, public RefCounted
     /** Returns the number of destination registers. */
     size_t numDestRegs() const { return numDests(); }
 
-    // the following are used to track physical register usage
+    size_t
-    // for machines with separate int & FP reg files
+    numDestRegs(RegClassType type) const
-    int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
-    int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
-    int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
-    int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
-    int8_t
-    numVecElemDestRegs() const
     {
-        return staticInst->numVecElemDestRegs();
+        return staticInst->numDestRegs(type);
-    }
-    int8_t
-    numVecPredDestRegs() const
-    {
-        return staticInst->numVecPredDestRegs();
     }
 
     /** Returns the logical register index of the i'th destination register. */

src/cpu/o3/rename.cc

@@ -656,12 +656,12 @@ Rename::renameInsts(ThreadID tid)
 
         // Check here to make sure there are enough destination registers
         // to rename to.  Otherwise block.
-        if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
+        if (!renameMap[tid]->canRename(inst->numDestRegs(IntRegClass),
-                                       inst->numFPDestRegs(),
+                                       inst->numDestRegs(FloatRegClass),
-                                       inst->numVecDestRegs(),
+                                       inst->numDestRegs(VecRegClass),
-                                       inst->numVecElemDestRegs(),
+                                       inst->numDestRegs(VecElemClass),
-                                       inst->numVecPredDestRegs(),
+                                       inst->numDestRegs(VecPredRegClass),
-                                       inst->numCCDestRegs())) {
+                                       inst->numDestRegs(CCRegClass))) {
             DPRINTF(Rename,
                     "Blocking due to "
                     " lack of free physical registers to rename to.\n");

src/cpu/static_inst.hh

@@ -115,36 +115,19 @@ class StaticInst : public RefCounted, public StaticInstFlags
   public:
 
     /// @name Register information.
-    /// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
+    /// The sum of the different numDestRegs([type])-s equals numDestRegs().
-    /// numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().
+    /// The per-type function is used to track physical register usage.
-    /// The former two functions are used to track physical register usage for
-    /// machines with separate int & FP reg files, the next three are for
-    /// machines with vector and predicate register files.
     //@{
     /// Number of source registers.
     uint8_t numSrcRegs()  const { return _numSrcRegs; }
     /// Number of destination registers.
     uint8_t numDestRegs() const { return _numDestRegs; }
-    /// Number of floating-point destination regs.
+    /// Number of destination registers of a particular type.
-    uint8_t numFPDestRegs() const { return _numTypedDestRegs[FloatRegClass]; }
-    /// Number of integer destination regs.
-    uint8_t numIntDestRegs() const { return _numTypedDestRegs[IntRegClass]; }
-    /// Number of vector destination regs.
-    uint8_t numVecDestRegs() const { return _numTypedDestRegs[VecRegClass]; }
-    /// Number of vector element destination regs.
     uint8_t
-    numVecElemDestRegs() const
+    numDestRegs(RegClassType type) const
     {
-        return _numTypedDestRegs[VecElemClass];
+        return _numTypedDestRegs[type];
     }
-    /// Number of predicate destination regs.
-    uint8_t
-    numVecPredDestRegs() const
-    {
-        return _numTypedDestRegs[VecPredRegClass];
-    }
-    /// Number of coprocesor destination regs.
-    uint8_t numCCDestRegs() const { return _numTypedDestRegs[CCRegClass]; }
     //@}
 
     /// @name Flag accessors.