stats: Update stats for CPU and cache changes
This patch updates the stats to reflect the fixes and changes to the CPU (mainly the o3), and the caches.
This commit is contained in:
Andreas Hansson
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@@ -1,16 +1,16 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.054241 # Number of seconds simulated
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sim_ticks 54240661000 # Number of ticks simulated
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final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.054141 # Number of seconds simulated
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sim_ticks 54141000000 # Number of ticks simulated
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final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1753346 # Simulator instruction rate (inst/s)
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host_op_rate 1765935 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1049669772 # Simulator tick rate (ticks/s)
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host_mem_usage 433744 # Number of bytes of host memory used
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host_seconds 51.67 # Real time elapsed on the host
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host_inst_rate 1737374 # Simulator instruction rate (inst/s)
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host_op_rate 1746027 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1038196846 # Simulator tick rate (ticks/s)
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host_mem_usage 439336 # Number of bytes of host memory used
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host_seconds 52.15 # Real time elapsed on the host
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sim_insts 90602407 # Number of instructions simulated
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sim_ops 91252960 # Number of ops (including micro ops) simulated
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sim_ops 91053638 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
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@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 431323080 # Nu
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system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory
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system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 22553294 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 130384064 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 7952024773 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1659577821 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 9611602595 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 7952024773 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 7952024773 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 348597116 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 348597116 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 7952024773 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2008174937 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 9960199711 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 9960199711 # Throughput (bytes/s)
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system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 9978534124 # Throughput (bytes/s)
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system.membus.data_through_bus 540247816 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu_clk_domain.clock 500 # Clock period in ticks
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@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 442 # Number of system calls
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system.cpu.numCycles 108481323 # number of cpu cycles simulated
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system.cpu.numCycles 108282001 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 90602407 # Number of instructions committed
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system.cpu.committedOps 91252960 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
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system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
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system.cpu.num_func_calls 112245 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls
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system.cpu.num_int_insts 72525674 # number of integer instructions
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system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
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system.cpu.num_int_insts 72326352 # number of integer instructions
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system.cpu.num_fp_insts 48 # number of float instructions
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system.cpu.num_int_register_reads 396967282 # number of times the integer registers were read
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system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
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system.cpu.num_int_register_reads 124257699 # number of times the integer registers were read
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system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
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system.cpu.num_mem_refs 27318810 # number of memory refs
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system.cpu.num_load_insts 22573966 # Number of load instructions
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system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read
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system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
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system.cpu.num_mem_refs 27220755 # number of memory refs
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system.cpu.num_load_insts 22475911 # Number of load instructions
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system.cpu.num_store_insts 4744844 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 108481323 # Number of busy cycles
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system.cpu.num_busy_cycles 108282001 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.Branches 18732304 # Number of branches fetched
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system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction
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system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction
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system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction
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system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction
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system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction
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system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
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system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
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system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
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system.cpu.op_class::total 91253402 # Class of executed instruction
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system.cpu.op_class::total 91054080 # Class of executed instruction
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---------- End Simulation Statistics ----------
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@@ -1,16 +1,16 @@
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.147136 # Number of seconds simulated
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sim_ticks 147135976000 # Number of ticks simulated
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final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_seconds 0.147041 # Number of seconds simulated
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sim_ticks 147041218000 # Number of ticks simulated
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final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 805246 # Simulator instruction rate (inst/s)
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host_op_rate 811020 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1308067541 # Simulator tick rate (ticks/s)
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host_mem_usage 443480 # Number of bytes of host memory used
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host_seconds 112.48 # Real time elapsed on the host
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host_inst_rate 1067718 # Simulator instruction rate (inst/s)
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host_op_rate 1073024 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1733318334 # Simulator tick rate (ticks/s)
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host_mem_usage 449084 # Number of bytes of host memory used
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host_seconds 84.83 # Real time elapsed on the host
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sim_insts 90576861 # Number of instructions simulated
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sim_ops 91226312 # Number of ops (including micro ops) simulated
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sim_ops 91026990 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
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@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 36992 # Nu
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system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 251414 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 6421054 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 6672467 # Total read bandwidth from this memory (bytes/s)
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||||
system.physmem.bw_inst_read::cpu.inst 251414 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 251414 # Instruction read bandwidth from this memory (bytes/s)
|
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system.physmem.bw_total::cpu.inst 251414 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 6421054 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6672467 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 6672467 # Throughput (bytes/s)
|
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system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 6676767 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 792 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 14548 # Transaction distribution
|
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@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
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system.membus.tot_pkt_size::total 981760 # Cumulative packet size per connected master and slave (bytes)
|
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system.membus.data_through_bus 981760 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 15340000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks)
|
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system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -130,77 +130,79 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 442 # Number of system calls
|
||||
system.cpu.numCycles 294271952 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 294082436 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 90576861 # Number of instructions committed
|
||||
system.cpu.committedOps 91226312 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses
|
||||
system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 112245 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72525674 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 15520157 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 72326352 # number of integer instructions
|
||||
system.cpu.num_fp_insts 48 # number of float instructions
|
||||
system.cpu.num_int_register_reads 464618159 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 106840357 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 124237033 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 54 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 30 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27318810 # number of memory refs
|
||||
system.cpu.num_load_insts 22573966 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 27220755 # number of memory refs
|
||||
system.cpu.num_load_insts 22475911 # Number of load instructions
|
||||
system.cpu.num_store_insts 4744844 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 294271952 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 294082436 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 18732304 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 63924095 70.05% 70.05% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10474 0.01% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.06% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 22573966 24.74% 94.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 4744844 5.20% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 91253402 # Class of executed instruction
|
||||
system.cpu.op_class::total 91054080 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 2 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.071144 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses
|
||||
@@ -217,12 +219,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n
|
||||
system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 599 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32063000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32063000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32063000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32063000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32063000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses
|
||||
@@ -235,12 +237,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006
|
||||
system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53527.545910 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53527.545910 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -255,43 +257,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599
|
||||
system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51527.545910 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 9565.271881 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8876.925013 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.124137 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.222731 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1468 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses
|
||||
@@ -320,17 +322,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 15340 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30056000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11128000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 41184000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 756496000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30056000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 767624000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 797680000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30056000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 767624000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 797680000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses)
|
||||
@@ -355,17 +357,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -420,78 +422,86 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 942702 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3565.217259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26345364 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 27.825750 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1322 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2583 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1355 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2550 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 55531122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55531122 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 55347598 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 55347598 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 21556948 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 21556948 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 507 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 507 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 26245320 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26245320 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 26245827 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26245827 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 900187 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 900187 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 946798 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 946796 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 946799 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 510 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 27192116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 27192116 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 27192626 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 27192626 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.040085 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -502,40 +512,54 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 942334 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 900186 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 946795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 821979690 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 822509400 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 942334 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.290499 # Number of seconds simulated
|
||||
sim_ticks 290498967000 # Number of ticks simulated
|
||||
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.279362 # Number of seconds simulated
|
||||
sim_ticks 279362297500 # Number of ticks simulated
|
||||
final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1775828 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2001536 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1018347697 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304924 # Number of bytes of host memory used
|
||||
host_seconds 285.27 # Real time elapsed on the host
|
||||
host_inst_rate 1833232 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1985632 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1010964168 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309500 # Number of bytes of host memory used
|
||||
host_seconds 276.33 # Real time elapsed on the host
|
||||
sim_insts 506581607 # Number of instructions simulated
|
||||
sim_ops 570968167 # Number of ops (including micro ops) simulated
|
||||
sim_ops 548694828 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
|
||||
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 2066445500 # Nu
|
||||
system.physmem.bytes_written::cpu.data 216067624 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 216067624 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 516611375 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125228857 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 641840232 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 115591527 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 632202902 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 55727847 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7113434933 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1455608278 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8569043211 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7113434933 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7113434933 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 743781041 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 743781041 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7113434933 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2199389318 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9312824252 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9312824252 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7397009255 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1513635536 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8910644791 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7397009255 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7397009255 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 773431583 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 773431583 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7397009255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2287067119 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9684076374 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9684076374 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2705365825 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 580997935 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 558724596 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 506581607 # Number of instructions committed
|
||||
system.cpu.committedOps 570968167 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
|
||||
system.cpu.committedOps 548694828 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727695 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 448454356 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2482508148 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 749039746 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890034 # number of memory refs
|
||||
system.cpu.num_load_insts 126029555 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 1634230247 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 172745235 # number of memory refs
|
||||
system.cpu.num_load_insts 115884756 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 580997935 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 558724596 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548301 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 570968717 # Class of executed instruction
|
||||
system.cpu.op_class::total 548695378 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.717366 # Number of seconds simulated
|
||||
sim_ticks 717366012000 # Number of ticks simulated
|
||||
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.707539 # Number of seconds simulated
|
||||
sim_ticks 707539023000 # Number of ticks simulated
|
||||
final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 879063 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 990556 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1248765490 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313636 # Number of bytes of host memory used
|
||||
host_seconds 574.46 # Real time elapsed on the host
|
||||
host_inst_rate 1172742 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1270027 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1643133313 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319240 # Number of bytes of host memory used
|
||||
host_seconds 430.60 # Real time elapsed on the host
|
||||
sim_insts 504986853 # Number of instructions simulated
|
||||
sim_ops 569034839 # Number of ops (including micro ops) simulated
|
||||
sim_ops 546878104 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
|
||||
@@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 139879 # Nu
|
||||
system.physmem.num_reads::total 142649 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 247126 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12479342 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12726469 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 247126 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 247126 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8560472 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8560472 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8560472 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 247126 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12479342 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21286941 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 21286941 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 21582595 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 41855 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 41855 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 95953 # Transaction distribution
|
||||
@@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 15270528 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 15270528 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1006226000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -138,79 +138,81 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 548 # Number of system calls
|
||||
system.cpu.numCycles 1434732024 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1415078046 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 504986853 # Number of instructions committed
|
||||
system.cpu.committedOps 569034839 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses
|
||||
system.cpu.committedOps 546878104 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 448454356 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 19311615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 470727695 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 90667196 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 448454356 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2861859644 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 646169352 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 748355652 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 290003067 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 182890034 # number of memory refs
|
||||
system.cpu.num_load_insts 126029555 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 1984297856 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 344080722 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 172745235 # number of memory refs
|
||||
system.cpu.num_load_insts 115884756 # Number of load instructions
|
||||
system.cpu.num_store_insts 56860479 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1434732024 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1415078046 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 121548301 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 387739461 67.91% 67.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.97% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 126029555 22.07% 90.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860479 9.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 375610921 68.46% 68.46% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 115884756 21.12% 89.64% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 56860479 10.36% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 570968717 # Class of executed instruction
|
||||
system.cpu.op_class::total 548695378 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 9788 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 982.663229 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses
|
||||
@@ -226,12 +228,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n
|
||||
system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 11521 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266195000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 266195000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 266195000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 266195000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 266195000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 266195000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses
|
||||
@@ -244,12 +246,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022
|
||||
system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23105.199201 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23105.199201 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23105.199201 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23105.199201 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23105.199201 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -264,38 +266,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521
|
||||
system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243153000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243153000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243153000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243153000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243153000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243153000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21105.199201 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21105.199201 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 109895 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 27243.192324 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 343698539000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23381.854289 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.865470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3573.472565 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id
|
||||
@@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 142649 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144122000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2033729000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2177851000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5241304000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5241304000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144122000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7275033000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7419155000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144122000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7275033000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7419155000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
|
||||
@@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52029.602888 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52033.491109 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52033.233783 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.158740 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.158740 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52009.863371 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52029.602888 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52009.472473 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52009.863371 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110882000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564709000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675591000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110882000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596485000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5707367000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110882000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596485000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5707367000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses
|
||||
@@ -417,27 +419,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40029.602888 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.491109 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.233783 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40029.602888 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1134822 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4065.297446 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 179817786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 157.884752 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
@@ -445,64 +447,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 343
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 343777666 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 343777666 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 113317758 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 113317758 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 2570 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 2570 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176840704 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 167200804 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 167200804 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 167203374 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 167203374 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 782657 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 782657 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1138917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 2571 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 2571 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168339721 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168339721 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168342292 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168342292 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.006859 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000389 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000389 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -513,40 +523,48 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1064905 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782657 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 782657 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000389 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000389 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 197642506 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 200387557 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 1064905 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,14 +1,14 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.219644 # Number of seconds simulated
|
||||
sim_ticks 219644167500 # Number of ticks simulated
|
||||
final_tick 219644167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.220941 # Number of seconds simulated
|
||||
sim_ticks 220941341500 # Number of ticks simulated
|
||||
final_tick 220941341500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 184210 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 184210 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 101490439 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 247040 # Number of bytes of host memory used
|
||||
host_seconds 2164.19 # Real time elapsed on the host
|
||||
host_inst_rate 303038 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 303038 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 167944827 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273400 # Number of bytes of host memory used
|
||||
host_seconds 1315.56 # Real time elapsed on the host
|
||||
sim_insts 398664665 # Number of instructions simulated
|
||||
sim_ops 398664665 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 249408 # Nu
|
||||
system.physmem.bytes_inst_read::total 249408 # Number of instructions bytes read from this memory
|
||||
system.physmem.num_reads::cpu.inst 7875 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 7875 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 2294620 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2294620 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1135509 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1135509 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2294620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2294620 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 2281148 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2281148 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1128843 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1128843 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2281148 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 2281148 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.readReqs 7875 # Number of read requests accepted
|
||||
system.physmem.writeReqs 0 # Number of write requests accepted
|
||||
system.physmem.readBursts 7875 # Number of DRAM read bursts, including those serviced by the write queue
|
||||
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
|
||||
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
||||
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
||||
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
||||
system.physmem.totGap 219644086000 # Total gap between requests
|
||||
system.physmem.totGap 220941260000 # Total gap between requests
|
||||
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
||||
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
||||
@@ -86,8 +86,8 @@ system.physmem.writePktSize::3 0 # Wr
|
||||
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
||||
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
||||
system.physmem.rdQLenPdf::0 6822 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 970 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::0 6820 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::1 972 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
|
||||
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
|
||||
@@ -182,29 +182,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
|
||||
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
||||
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
||||
system.physmem.bytesPerActivate::samples 1515 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 331.828383 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 199.155331 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 333.926802 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 511 33.73% 33.73% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 341 22.51% 56.24% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 189 12.48% 68.71% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 107 7.06% 75.78% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 50 3.30% 79.08% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 60 3.96% 83.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 36 2.38% 85.41% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 30 1.98% 87.39% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 191 12.61% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1515 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 51832750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 199489000 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.bytesPerActivate::samples 1518 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::mean 330.160738 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::gmean 197.894458 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::stdev 332.998951 # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::0-127 519 34.19% 34.19% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::128-255 336 22.13% 56.32% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::256-383 186 12.25% 68.58% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::384-511 110 7.25% 75.82% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::512-639 56 3.69% 79.51% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::640-767 56 3.69% 83.20% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::768-895 37 2.44% 85.64% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::896-1023 28 1.84% 87.48% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 190 12.52% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 1518 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 52730250 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 200386500 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 39375000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6581.94 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6695.90 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25331.94 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.29 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgMemAccLat 25445.90 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 2.28 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.29 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 2.28 # Average system read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
||||
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
||||
system.physmem.busUtil 0.02 # Data bus utilization in percentage
|
||||
@@ -212,18 +212,18 @@ system.physmem.busUtilRead 0.02 # Da
|
||||
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
||||
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
||||
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
||||
system.physmem.readRowHits 6354 # Number of row buffer hits during reads
|
||||
system.physmem.readRowHits 6348 # Number of row buffer hits during reads
|
||||
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
||||
system.physmem.readRowHitRate 80.69 # Row buffer hit rate for reads
|
||||
system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 27891312.51 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.69 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 210595847500 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 7334340000 # Time in different power states
|
||||
system.physmem.avgGap 28056033.02 # Average gap between requests
|
||||
system.physmem.pageHitRate 80.61 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 211835989750 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 7377500000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1712418250 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1721627750 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 2294620 # Throughput (bytes/s)
|
||||
system.membus.throughput 2281148 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 4737 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 4737 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 3138 # Transaction distribution
|
||||
@@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 504000 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 504000 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 9401500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 9511500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 73916250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 74010500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 46223200 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26710359 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1014875 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25598344 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 21333887 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 46221231 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 26710053 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 1012987 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 25408308 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 21330923 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 83.340887 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8326899 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 83.952552 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 8326726 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 95595217 # DTB read hits
|
||||
system.cpu.dtb.read_misses 114 # DTB read misses
|
||||
system.cpu.dtb.read_hits 95595776 # DTB read hits
|
||||
system.cpu.dtb.read_misses 118 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 95595331 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73605959 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 95595894 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 73604420 # DTB write hits
|
||||
system.cpu.dtb.write_misses 858 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 73606817 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 169201176 # DTB hits
|
||||
system.cpu.dtb.data_misses 972 # DTB misses
|
||||
system.cpu.dtb.write_accesses 73605278 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 169200196 # DTB hits
|
||||
system.cpu.dtb.data_misses 976 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 169202148 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 98054052 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1240 # ITB misses
|
||||
system.cpu.dtb.data_accesses 169201172 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 98242303 # ITB hits
|
||||
system.cpu.itb.fetch_misses 1225 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 98055292 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 98243528 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
@@ -281,70 +281,70 @@ system.cpu.itb.data_misses 0 # DT
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 215 # Number of system calls
|
||||
system.cpu.numCycles 439288335 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 441882683 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 398664665 # Number of instructions committed
|
||||
system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 4458110 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 4446127 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.101899 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.907524 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 435056382 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 4231953 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.cpi 1.108407 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.902196 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 437732113 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 4150570 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 3195 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1919.689869 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 98048879 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1919.708567 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 98237130 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 5173 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18953.968490 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18990.359559 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.689869 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937349 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937349 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1919.708567 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.937358 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.937358 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 200 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 398 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1282 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 196113277 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 196113277 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 98048879 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 98048879 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 98048879 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 98048879 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 98048879 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 98048879 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 196489779 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 196489779 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 98237130 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 98237130 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 98237130 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 98237130 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 98237130 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 98237130 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 5173 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 5173 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 5173 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 5173 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 5173 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 5173 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293884750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 293884750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 293884750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 293884750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 293884750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 293884750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98054052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 98054052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 98054052 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 98054052 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 98054052 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 98054052 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 293554750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 293554750 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 293554750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 293554750 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 293554750 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 293554750 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 98242303 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 98242303 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 98242303 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 98242303 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 98242303 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 98242303 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000053 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000053 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000053 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56811.279722 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56811.279722 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56811.279722 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56811.279722 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56811.279722 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56747.486951 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 56747.486951 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 56747.486951 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -359,26 +359,26 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5173
|
||||
system.cpu.icache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 5173 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 5173 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281914250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281914250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281914250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281914250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281914250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281914250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281585250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281585250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281585250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281585250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281585250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281585250 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000053 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000053 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000053 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54497.245312 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54497.245312 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54497.245312 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54497.245312 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54433.645853 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54433.645853 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 54433.645853 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 2911473 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 2894379 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 6139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 6139 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 654 # Transaction distribution
|
||||
@@ -394,24 +394,24 @@ system.cpu.toL2Bus.data_through_bus 639488 # To
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 5650000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 8571750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 8571250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6975500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 6974750 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 4427.544414 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 4427.627395 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1491 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 5274 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.282708 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 373.069820 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.474595 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011385 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123733 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.135118 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 373.083919 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4054.543476 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123735 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.135120 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 5274 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4444 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160950 # Percentage of cache occupancy per task id
|
||||
@@ -435,14 +435,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 7875 #
|
||||
system.cpu.l2cache.demand_misses::total 7875 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 7875 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 7875 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325631750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 325631750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212036500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 212036500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 537668250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 537668250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 537668250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 537668250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 325767500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 325767500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 212904500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 212904500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 538672000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 538672000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 538672000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 538672000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 6139 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 6139 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 654 # number of Writeback accesses(hits+misses)
|
||||
@@ -461,14 +461,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.843328
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.843328 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.843328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.843328 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68742.189149 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68742.189149 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67570.586361 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67570.586361 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68275.333333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68275.333333 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68275.333333 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68770.846527 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68770.846527 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 67847.195666 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67847.195666 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68402.793651 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -485,14 +485,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 7875
|
||||
system.cpu.l2cache.demand_mshr_misses::total 7875 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 7875 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266250750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266250750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 172336000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 172336000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438586750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 438586750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438586750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 438586750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 266387000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 266387000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 173110500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 173110500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 439497500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 439497500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 439497500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 439497500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.771624 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771624 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.980932 # mshr miss rate for ReadExReq accesses
|
||||
@@ -501,65 +501,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.843328
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.843328 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.843328 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.843328 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56206.618113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56206.618113 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54919.056724 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54919.056724 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55693.555556 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55693.555556 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56235.381043 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56235.381043 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55165.869981 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55165.869981 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55809.206349 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 771 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3291.682067 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168006905 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3291.748201 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168007181 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40337.792317 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 40337.858583 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.682067 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.803633 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803633 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 3291.748201 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.803649 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.803649 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 336032209 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336032209 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 94492115 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94492115 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 73514790 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514790 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 168006905 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168006905 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 168006905 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168006905 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 1177 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1177 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 5940 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5940 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.inst 7117 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7117 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 7117 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7117 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 80734750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 80734750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 392862000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 392862000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 473596750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 473596750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 473596750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 473596750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 94493292 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94493292 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.tags.tag_accesses 336032765 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336032765 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 94492394 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94492394 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 73514787 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 73514787 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 168007181 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168007181 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 168007181 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168007181 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 1176 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1176 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 5943 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 5943 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.inst 7119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.inst 7119 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 7119 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 81035500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 81035500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 393767750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 393767750 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 474803250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 474803250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 474803250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 474803250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 94493570 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94493570 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 168014022 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168014022 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 168014022 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168014022 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 168014300 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168014300 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 168014300 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168014300 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000012 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000012 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000081 # miss rate for WriteReq accesses
|
||||
@@ -568,14 +568,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.000042
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68593.670348 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68593.670348 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66138.383838 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66138.383838 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66544.435858 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66544.435858 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66544.435858 # average overall miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 68907.738095 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 68907.738095 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 66257.403668 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 66257.403668 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 66695.217025 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -588,28 +588,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu
|
||||
system.cpu.dcache.writebacks::total 654 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 208 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2744 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2744 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 2952 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2952 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 2952 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2952 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 2746 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.WriteReq_mshr_hits::total 2746 # number of WriteReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.inst 2954 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.inst 2954 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 968 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 968 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 3197 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 3197 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.inst 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.inst 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64078250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64078250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 215682250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 215682250 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 279760500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 279760500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 279760500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 279760500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 64480250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 64480250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 216613000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 216613000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 281093250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 281093250 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 281093250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 281093250 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000043 # mshr miss rate for WriteReq accesses
|
||||
@@ -618,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.000025
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66128.224974 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66128.224974 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67485.059449 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67485.059449 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67169.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67169.387755 # average overall mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 66611.828512 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66611.828512 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67755.082890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67755.082890 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 67489.375750 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.199332 # Nu
|
||||
sim_ticks 199332411500 # Number of ticks simulated
|
||||
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2589605 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2589605 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1294803220 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 262692 # Number of bytes of host memory used
|
||||
host_seconds 153.95 # Real time elapsed on the host
|
||||
host_inst_rate 3159999 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3159998 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1579999901 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 261616 # Number of bytes of host memory used
|
||||
host_seconds 126.16 # Real time elapsed on the host
|
||||
sim_insts 398664595 # Number of instructions simulated
|
||||
sim_ops 398664595 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587532 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 145805196 36.57% 42.37% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 141652555 35.53% 41.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.567335 # Nu
|
||||
sim_ticks 567335093000 # Number of ticks simulated
|
||||
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1080224 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1080224 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1537254294 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271408 # Number of bytes of host memory used
|
||||
host_seconds 369.06 # Real time elapsed on the host
|
||||
host_inst_rate 1556013 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1556013 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2214344764 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 270340 # Number of bytes of host memory used
|
||||
host_seconds 256.21 # Real time elapsed on the host
|
||||
sim_insts 398664609 # Number of instructions simulated
|
||||
sim_ops 398664609 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 44587535 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 23123356 5.80% 5.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 145805208 36.57% 42.37% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 42.91% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 31467419 7.89% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 141652567 35.53% 41.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2124322 0.53% 41.86% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 41.86% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 35620060 8.93% 50.80% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 7072549 1.77% 52.57% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2735231 0.69% 53.26% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 16498021 4.14% 57.40% # Class of executed instruction
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,42 +1,42 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.212344 # Number of seconds simulated
|
||||
sim_ticks 212344043000 # Number of ticks simulated
|
||||
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.201717 # Number of seconds simulated
|
||||
sim_ticks 201717313500 # Number of ticks simulated
|
||||
final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1152169 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1472992 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 896053064 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309060 # Number of bytes of host memory used
|
||||
host_seconds 236.98 # Real time elapsed on the host
|
||||
sim_insts 273037663 # Number of instructions simulated
|
||||
sim_ops 349065399 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1169681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1404332 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 864148101 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314684 # Number of bytes of host memory used
|
||||
host_seconds 233.43 # Real time elapsed on the host
|
||||
sim_insts 273037594 # Number of instructions simulated
|
||||
sim_ops 327811949 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1394641404 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1394641404 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 400047783 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 400047783 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 348660351 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 94582505 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 443242856 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 82063572 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 82063572 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6567838609 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2263822715 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8831661324 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6567838609 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6567838609 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1883960470 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1883960470 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6567838609 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4147783185 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10715621794 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10715621794 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2275398455 # Total data (bytes)
|
||||
system.physmem.bytes_read::cpu.inst 1394641092 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 1875350308 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 1394641092 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 1394641092 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 348660273 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 434960784 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6913839312 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2383083572 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9296922884 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6913839312 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6913839312 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1983209850 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1983209850 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6913839312 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4366293422 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 11280132734 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 11280132734 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 2275398071 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 424688087 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 403434628 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 273037663 # Number of instructions committed
|
||||
system.cpu.committedOps 349065399 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 273037594 # Number of instructions committed
|
||||
system.cpu.committedOps 327811949 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 279584918 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 258331481 # number of integer instructions
|
||||
system.cpu.num_fp_insts 114216705 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2254222459 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 251197905 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 1174407516 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 177024356 # number of memory refs
|
||||
system.cpu.num_load_insts 94648757 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_cc_register_reads 985884623 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 168107829 # number of memory refs
|
||||
system.cpu.num_load_insts 85732235 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375594 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 424688087 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 403434628 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563502 # Number of branches fetched
|
||||
system.cpu.Branches 30563490 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 116649415 33.42% 33.42% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 104312492 31.82% 31.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 85732235 26.15% 74.87% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375594 25.13% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 349065594 # Class of executed instruction
|
||||
system.cpu.op_class::total 327812144 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.525834 # Number of seconds simulated
|
||||
sim_ticks 525834342000 # Number of ticks simulated
|
||||
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.517235 # Number of seconds simulated
|
||||
sim_ticks 517235411000 # Number of ticks simulated
|
||||
final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 605985 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 774729 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1168322503 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318808 # Number of bytes of host memory used
|
||||
host_seconds 450.08 # Real time elapsed on the host
|
||||
sim_insts 272739283 # Number of instructions simulated
|
||||
sim_ops 348687122 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 749544 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 899855 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1421469107 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 324416 # Number of bytes of host memory used
|
||||
host_seconds 363.87 # Real time elapsed on the host
|
||||
sim_insts 272739285 # Number of instructions simulated
|
||||
sim_ops 327433743 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
|
||||
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 166976 # Nu
|
||||
system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 831532 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 322824 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 522532 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 845356 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 322824 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 322824 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 322824 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 522532 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 845356 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 845356 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 3976 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 2856 # Transaction distribution
|
||||
@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 437248 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 437248 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 191 # Number of system calls
|
||||
system.cpu.numCycles 1051668684 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1034470822 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 272739283 # Number of instructions committed
|
||||
system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 272739285 # Number of instructions committed
|
||||
system.cpu.committedOps 327433743 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 12448615 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 279584917 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 258331537 # number of integer instructions
|
||||
system.cpu.num_fp_insts 114216705 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2579483474 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 1215888421 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 177024356 # number of memory refs
|
||||
system.cpu.num_load_insts 94648757 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 1242915500 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 168107847 # number of memory refs
|
||||
system.cpu.num_load_insts 85732248 # Number of load instructions
|
||||
system.cpu.num_store_insts 82375599 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1051668684 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1034470822 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 30563501 # Number of branches fetched
|
||||
system.cpu.Branches 30563502 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 116649413 33.42% 33.42% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.61% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 34.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 1.89% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 35.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.28% 38.20% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.89% 39.09% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.45% 39.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 5.63% 45.17% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.04% 47.21% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.02% 49.24% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 49.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 94648757 27.11% 76.40% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375599 23.60% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 104312543 31.82% 31.82% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 85732248 26.15% 74.87% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 82375599 25.13% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 349065592 # Class of executed instruction
|
||||
system.cpu.op_class::total 327812213 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 13796 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
@@ -204,44 +206,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 26
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 348644747 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 697336307 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 697336307 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 348644749 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 348644749 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 348644749 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 348644749 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 348644749 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 348644749 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15603 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 348660352 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 348660352 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 348660352 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -256,38 +258,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603
|
||||
system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.106438 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
|
||||
@@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 6832 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
|
||||
@@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -386,17 +388,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses
|
||||
@@ -408,92 +410,100 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1332 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 336732670 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 336732670 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 86233963 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 54059 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 176619809 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 168337827 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1604 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4478 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 3 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 3 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 4479 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 4479 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 54062 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 168288244 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 168342306 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000019 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000019 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000055 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.000055 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000027 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -504,40 +514,54 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 998 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1603 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000055 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000055 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 2608205 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,64 +1,64 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.004711 # Number of seconds simulated
|
||||
sim_ticks 1004710587000 # Number of ticks simulated
|
||||
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.464395 # Number of seconds simulated
|
||||
sim_ticks 464394627000 # Number of ticks simulated
|
||||
final_tick 464394627000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2670371 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2670371 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1335473702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265688 # Number of bytes of host memory used
|
||||
host_seconds 752.33 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1843860 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1843860 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 922130037 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 234352 # Number of bytes of host memory used
|
||||
host_seconds 503.61 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 8037684280 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 8037684280 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 1586125963 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 1586125963 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2009421070 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 511070026 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2520491096 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 210794896 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 210794896 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7999999586 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3552681501 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 11552681087 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7999999586 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7999999586 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1578689409 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1578689409 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7999999586 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5131370910 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13131370496 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13131370496 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 13193226959 # Total data (bytes)
|
||||
system.physmem.bytes_read::cpu.inst 3715156600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1657129778 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 5372286378 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 3715156600 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 3715156600 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 737675461 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 737675461 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 928789150 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 237510597 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1166299747 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 98301200 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 98301200 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7999999104 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3568365527 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 11568364631 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7999999104 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7999999104 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1588466830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1588466830 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7999999104 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5156832357 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 13156831461 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 13156831461 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 6109961839 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 511070026 # DTB read hits
|
||||
system.cpu.dtb.read_misses 418884 # DTB read misses
|
||||
system.cpu.dtb.read_hits 237510597 # DTB read hits
|
||||
system.cpu.dtb.read_misses 194650 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14581 # DTB write misses
|
||||
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98301200 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6871 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 721864922 # DTB hits
|
||||
system.cpu.dtb.data_misses 433465 # DTB misses
|
||||
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335811797 # DTB hits
|
||||
system.cpu.dtb.data_misses 201521 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2009421070 # ITB hits
|
||||
system.cpu.dtb.data_accesses 336013318 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 928789150 # ITB hits
|
||||
system.cpu.itb.fetch_misses 105 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2009421175 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 928789255 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
@@ -71,64 +71,64 @@ system.cpu.itb.data_hits 0 # DT
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 39 # Number of system calls
|
||||
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 928789255 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2008987605 # Number of instructions committed
|
||||
system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1779374816 # number of integer instructions
|
||||
system.cpu.num_fp_insts 71831671 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 722298387 # number of memory refs
|
||||
system.cpu.num_load_insts 511488910 # Number of load instructions
|
||||
system.cpu.num_store_insts 210809477 # Number of store instructions
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 822136244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 33439365 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 336013318 # number of memory refs
|
||||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 2009421175 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 928789255 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 266706457 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2009421070 # Class of executed instruction
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,78 +1,78 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.769740 # Number of seconds simulated
|
||||
sim_ticks 2769739533000 # Number of ticks simulated
|
||||
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.286250 # Number of seconds simulated
|
||||
sim_ticks 1286249820000 # Number of ticks simulated
|
||||
final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1094265 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1094265 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1508635104 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 274392 # Number of bytes of host memory used
|
||||
host_seconds 1835.92 # Real time elapsed on the host
|
||||
sim_insts 2008987605 # Number of instructions simulated
|
||||
sim_ops 2008987605 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 839019 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 839019 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1162182391 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244120 # Number of bytes of host memory used
|
||||
host_seconds 1106.75 # Real time elapsed on the host
|
||||
sim_insts 928587629 # Number of instructions simulated
|
||||
sim_ops 928587629 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18465664 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18603456 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 137792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 137792 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4282112 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4282112 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 2153 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 473196 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 475349 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66908 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66908 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 49749 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 10934077 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 10983826 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 49749 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 49749 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1546034 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1546034 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1546034 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 49749 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 10934077 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 12529860 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 12529860 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 408476 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 408476 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66908 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66873 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66873 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1017606 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34704448 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34704448 # Total data (bytes)
|
||||
system.physmem.num_reads::cpu.data 288526 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 290679 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 107127 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 14356203 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 14463330 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 107127 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 107127 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 3317950 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 3317950 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 3317950 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 17781280 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 224031 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 224031 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66683 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66648 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66648 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22871168 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1077521000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 511070026 # DTB read hits
|
||||
system.cpu.dtb.read_misses 418884 # DTB read misses
|
||||
system.cpu.dtb.read_hits 237510597 # DTB read hits
|
||||
system.cpu.dtb.read_misses 194650 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 511488910 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 210794896 # DTB write hits
|
||||
system.cpu.dtb.write_misses 14581 # DTB write misses
|
||||
system.cpu.dtb.read_accesses 237705247 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 98301200 # DTB write hits
|
||||
system.cpu.dtb.write_misses 6871 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 210809477 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 721864922 # DTB hits
|
||||
system.cpu.dtb.data_misses 433465 # DTB misses
|
||||
system.cpu.dtb.write_accesses 98308071 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 335811797 # DTB hits
|
||||
system.cpu.dtb.data_misses 201521 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 722298387 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 2009421071 # ITB hits
|
||||
system.cpu.dtb.data_accesses 336013318 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 928789151 # ITB hits
|
||||
system.cpu.itb.fetch_misses 105 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 928789256 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
@@ -85,118 +85,118 @@ system.cpu.itb.data_hits 0 # DT
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 39 # Number of system calls
|
||||
system.cpu.numCycles 5539479066 # number of cpu cycles simulated
|
||||
system.cpu.workload.num_syscalls 37 # Number of system calls
|
||||
system.cpu.numCycles 2572499640 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 2008987605 # Number of instructions committed
|
||||
system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 172959296 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1779374816 # number of integer instructions
|
||||
system.cpu.num_fp_insts 71831671 # number of float instructions
|
||||
system.cpu.num_int_register_reads 2314712013 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1332688300 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 77066699 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 52280770 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 722298387 # number of memory refs
|
||||
system.cpu.num_load_insts 511488910 # Number of load instructions
|
||||
system.cpu.num_store_insts 210809477 # Number of store instructions
|
||||
system.cpu.committedInsts 928587629 # Number of instructions committed
|
||||
system.cpu.committedOps 928587629 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 822136244 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 33439365 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37048314 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 79645038 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 822136244 # number of integer instructions
|
||||
system.cpu.num_fp_insts 33439365 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1066359180 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 614731604 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 35725528 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 24235554 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 336013318 # number of memory refs
|
||||
system.cpu.num_load_insts 237705247 # Number of load instructions
|
||||
system.cpu.num_store_insts 98308071 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5539479066 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2572499640 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 266706457 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 185946986 9.25% 9.25% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1058512437 52.68% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 15158 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.93% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 27517120 1.37% 63.30% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 8254514 0.41% 63.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 6876464 0.34% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.05% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 511488910 25.45% 89.51% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 210809477 10.49% 100.00% # Class of executed instruction
|
||||
system.cpu.Branches 123111018 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 86206875 9.28% 9.28% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 486529511 52.38% 61.66% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 7040 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.67% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 13018262 1.40% 63.07% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 3826477 0.41% 63.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 3187663 0.34% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 4 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 237705247 25.59% 89.42% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 2009421070 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 9046 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1478.418050 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 2009410475 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 189638.587675 # Average number of references to valid blocks.
|
||||
system.cpu.op_class::total 928789150 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 4618 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 4018852738 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 4018852738 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 2009410475 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 2009410475 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 2009410475 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 10596 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 10596 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10596 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10596 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 228174000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 228174000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 228174000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 228174000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 228174000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 228174000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 2009421071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 2009421071 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 2009421071 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 2009421071 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 2009421071 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 2009421071 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21533.975085 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21533.975085 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21533.975085 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21533.975085 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21533.975085 # average overall miss latency
|
||||
system.cpu.icache.tags.tag_accesses 1857584470 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1857584470 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 928782983 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 928782983 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 928782983 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 928782983 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 928782983 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 928782983 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 6168 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 6168 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 6168 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 928789151 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 928789151 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 928789151 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000007 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -205,123 +205,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10596 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10596 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 206982000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 206982000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 206982000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 206982000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 206982000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 206982000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19533.975085 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19533.975085 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 6168 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 442570 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32706.854192 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1089464 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 475302 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.292151 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 257900 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1300.510334 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.518402 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31379.825456 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32732 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.929411 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.203190 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.309249 # miss rate for demand accesses
|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.203190 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.309249 # miss rate for overall accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -330,119 +330,119 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965717 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.007383 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.007344 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4095.197836 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 776432 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 999 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2416 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1445259988 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1445259988 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 720334778 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency
|
||||
system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 335031269 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 780528 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -451,60 +451,60 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 96129 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
|
||||
system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 91660 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 37822912 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1468788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1468788 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 96129 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 71952 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21192 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3156417 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3177609 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 678144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104081472 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 104759616 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 104759616 # Total data (bytes)
|
||||
system.cpu.toL2Bus.throughput 43704406 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69014 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12336 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652716 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1665052 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 394752 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55820032 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 56214784 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 56214784 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 914563500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 530838000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15894000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 9252000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2295216000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,42 +1,42 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.945613 # Number of seconds simulated
|
||||
sim_ticks 945613126000 # Number of ticks simulated
|
||||
final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.395727 # Number of seconds simulated
|
||||
sim_ticks 395726778000 # Number of ticks simulated
|
||||
final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1407956 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1917442 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 961716087 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309672 # Number of bytes of host memory used
|
||||
host_seconds 983.26 # Real time elapsed on the host
|
||||
sim_insts 1384381606 # Number of instructions simulated
|
||||
sim_ops 1885336358 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 935276 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1151448 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 577711928 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 250216 # Number of bytes of host memory used
|
||||
host_seconds 684.99 # Real time elapsed on the host
|
||||
sim_insts 640654410 # Number of instructions simulated
|
||||
sim_ops 788730069 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 5561086004 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 5561086004 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 1123958396 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 1123958396 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1390271501 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 620345398 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2010616899 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 276945663 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 276945663 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 5880931484 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2606145374 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8487076858 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5880931484 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5880931484 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1188602786 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1188602786 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 5880931484 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3794748160 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9675679644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9675679644 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 9149449674 # Total data (bytes)
|
||||
system.physmem.bytes_read::cpu.inst 2573511592 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 3718230108 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 2573511592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 2573511592 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 643377898 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 893713136 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6503253596 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2892699154 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9395952750 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6503253596 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6503253596 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1322421029 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1322421029 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6503253596 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 4215120183 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10718373779 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10718373779 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 4241547521 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -123,64 +123,66 @@ system.cpu.itb.inst_accesses 0 # IT
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
||||
system.cpu.numCycles 1891226253 # number of cpu cycles simulated
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 791453557 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1384381606 # Number of instructions committed
|
||||
system.cpu.committedOps 1885336358 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 80372855 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1653698868 # number of integer instructions
|
||||
system.cpu.num_fp_insts 52289415 # number of float instructions
|
||||
system.cpu.num_int_register_reads 8779152446 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 908382479 # number of memory refs
|
||||
system.cpu.num_load_insts 631387181 # Number of load instructions
|
||||
system.cpu.num_store_insts 276995298 # Number of store instructions
|
||||
system.cpu.committedInsts 640654410 # Number of instructions committed
|
||||
system.cpu.committedOps 788730069 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 682251400 # number of integer instructions
|
||||
system.cpu.num_fp_insts 24239771 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1320162254 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 2369173291 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 381221435 # number of memory refs
|
||||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1891226253 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 791453557 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 298259106 # Number of branches fetched
|
||||
system.cpu.Branches 137364859 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1885337770 # Class of executed instruction
|
||||
system.cpu.op_class::total 788730743 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,56 +1,56 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.326119 # Number of seconds simulated
|
||||
sim_ticks 2326118592000 # Number of ticks simulated
|
||||
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.043695 # Number of seconds simulated
|
||||
sim_ticks 1043695084000 # Number of ticks simulated
|
||||
final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 706219 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 958037 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1189016431 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318376 # Number of bytes of host memory used
|
||||
host_seconds 1956.34 # Real time elapsed on the host
|
||||
sim_insts 1381604339 # Number of instructions simulated
|
||||
sim_ops 1874244941 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 520727 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 639745 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 850028397 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259968 # Number of bytes of host memory used
|
||||
host_seconds 1227.84 # Real time elapsed on the host
|
||||
sim_insts 639366786 # Number of instructions simulated
|
||||
sim_ops 785501034 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 113472 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 113472 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 472383 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 474156 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 48782 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 12996978 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 13045760 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 48782 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 48782 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1818624 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1818624 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1818624 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 48782 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 12996978 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 14864384 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 14864384 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 408063 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 408063 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66099 # Transaction distribution
|
||||
system.physmem.bytes_read::cpu.inst 113280 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 18428288 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 18541568 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 113280 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 113280 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1770 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 287942 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 289712 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 108537 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 17656774 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 17765311 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 108537 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 108537 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4053168 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4053168 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4053168 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 108537 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 17656774 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 21818480 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 21818480 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 223619 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 223619 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 66098 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 66093 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExResp 66093 # Transaction distribution
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 1014411 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 34576320 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 34576320 # Total data (bytes)
|
||||
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 645522 # Packet count per connected master and slave (bytes)
|
||||
system.membus.pkt_count::total 645522 # Packet count per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22771840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.tot_pkt_size::total 22771840 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22771840 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 1069047000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -137,117 +137,119 @@ system.cpu.itb.inst_accesses 0 # IT
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1411 # Number of system calls
|
||||
system.cpu.numCycles 4652237184 # number of cpu cycles simulated
|
||||
system.cpu.workload.num_syscalls 673 # Number of system calls
|
||||
system.cpu.numCycles 2087390168 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1381604339 # Number of instructions committed
|
||||
system.cpu.committedOps 1874244941 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 80372855 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1653698868 # number of integer instructions
|
||||
system.cpu.num_fp_insts 52289415 # number of float instructions
|
||||
system.cpu.num_int_register_reads 10644316447 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1874331393 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 60540850 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 46777010 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 908382479 # number of memory refs
|
||||
system.cpu.num_load_insts 631387181 # Number of load instructions
|
||||
system.cpu.num_store_insts 276995298 # Number of store instructions
|
||||
system.cpu.committedInsts 639366786 # Number of instructions committed
|
||||
system.cpu.committedOps 785501034 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 37261296 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 682251400 # number of integer instructions
|
||||
system.cpu.num_fp_insts 24239771 # number of float instructions
|
||||
system.cpu.num_int_register_reads 1323974869 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 3116296057 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 381221435 # number of memory refs
|
||||
system.cpu.num_load_insts 252240938 # Number of load instructions
|
||||
system.cpu.num_store_insts 128980497 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4652237184 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 2087390168 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 298259106 # Number of branches fetched
|
||||
system.cpu.Branches 137364859 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 930023895 49.33% 49.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 11168279 0.59% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.92% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 1375288 0.07% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.99% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 6876469 0.36% 50.36% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 5501172 0.29% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 22010188 1.17% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.82% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 631387181 33.49% 85.31% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 276995298 14.69% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 385757466 48.91% 48.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 252240938 31.98% 83.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 128980497 16.35% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1885337770 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 18364 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1392.317060 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1390251699 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 19803 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 70204.095289 # Average number of references to valid blocks.
|
||||
system.cpu.op_class::total 788730743 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 8769 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 1390251699 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 1390251699 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 1390251699 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 19803 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 19803 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 19803 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 19803 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 19803 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 19803 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 331911000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 331911000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 331911000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 331911000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 331911000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 331911000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1390271502 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1390271502 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1390271502 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 1390271502 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 1390271502 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 1390271502 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000014 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000014 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000014 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000014 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000014 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16760.642327 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 16760.642327 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 16760.642327 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16760.642327 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 16760.642327 # average overall miss latency
|
||||
system.cpu.icache.tags.tag_accesses 1286766006 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 1286766006 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 643367691 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 643367691 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 643367691 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 643367691 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 643367691 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 643367691 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 10208 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 10208 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 10208 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 643377899 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 643377899 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 643377899 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -256,123 +258,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19803 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 19803 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 19803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 19803 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 19803 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 19803 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292305000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 292305000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 292305000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292305000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 292305000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000014 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000014 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000014 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14760.642327 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14760.642327 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 10208 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_misses::total 10208 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::cpu.inst 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 441378 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32692.891822 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1102614 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 474121 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.325596 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 256932 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 1298.141733 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.233408 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 31364.516681 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.995688 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1387 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31024 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1441 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 30967 # Occupied blocks per task id
|
||||
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|
||||
system.cpu.l2cache.tags.tag_accesses 13744605 # Number of tag accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.Writeback_hits::total 96257 # number of Writeback hits
|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_hits::cpu.inst 18030 # number of demand (read+write) hits
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_hits::cpu.data 1061270 # number of overall hits
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_misses::total 408063 # number of ReadReq misses
|
||||
system.cpu.l2cache.tags.tag_accesses 7430286 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 7430286 # Number of data accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.Writeback_hits::total 91561 # number of Writeback hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_hits::cpu.inst 8438 # number of overall hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1773 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 472383 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 474156 # number of overall misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3436836000 # number of ReadExReq miss cycles
|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_miss_latency::total 24656118000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 92202000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 24563916000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 24656118000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 19803 # number of ReadReq accesses(hits+misses)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.089532 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.278115 # miss rate for ReadReq accesses
|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908120 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.908120 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.089532 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.308012 # miss rate for demand accesses
|
||||
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|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.089532 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.308012 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.305227 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52003.384095 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.014704 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000.012654 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52003.384095 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000.012654 # average overall miss latency
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 1770 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 287942 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 289712 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 289712 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles
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||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_accesses::total 792350 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.173393 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311228 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.309282 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.953407 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.173393 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.368145 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.365636 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -381,127 +383,135 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 1773 # number of overall MSHR misses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16322526000 # number of ReadReq MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70926000 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.089532 # mshr miss rate for ReadReq accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308012 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.305227 # mshr miss rate for overall accesses
|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles
|
||||
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|
||||
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|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953407 # mshr miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.014704 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40003.384095 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1529557 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4094.947189 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 895757408 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1533653 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 584.067848 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.replacements 778046 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 568 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1040 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2341 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 591 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1036 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1796115775 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1796115775 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 895737438 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency
|
||||
system.cpu.dcache.tags.tag_accesses 759367050 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 759367050 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 249613198 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 249613198 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 128882154 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 128882154 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 3481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 3481 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 378495352 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 378495352 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 378498833 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 378498833 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 712681 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 712681 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 69323 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 69323 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 139 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 139 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 782004 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 782143 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 782143 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18582698000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 18582698000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 3677152000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 3677152000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 22259850000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 22259850000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 22259850000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 22259850000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 250325879 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 3620 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 3620 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 379277356 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 379277356 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 379280976 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 379280976 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002847 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.002847 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000538 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000538 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038398 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.038398 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.002062 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.002062 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26074.355848 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 26074.355848 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53043.751713 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53043.751713 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28465.135728 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 28465.135728 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28460.076994 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 28460.076994 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -510,60 +520,74 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 96257 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
|
||||
system.cpu.dcache.writebacks::writebacks 91561 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 91561 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712680 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 712680 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69323 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 69323 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038398 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038398 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 45389617 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 1480676 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 1480676 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 96257 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 72780 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39606 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3163563 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 3203169 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1267392 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104314240 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 105581632 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 105581632 # Total data (bytes)
|
||||
system.cpu.toL2Bus.throughput 54201945 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 91561 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExResp 69323 # Transaction distribution
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655845 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.pkt_count::total 1676261 # Packet count per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 653312 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55916992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.tot_pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.cpu.toL2Bus.data_through_bus 56570304 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 921113500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 29704500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer0.occupancy 15312000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 2300479500 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 1173213000 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu
|
||||
sim_ticks 44221003000 # Number of ticks simulated
|
||||
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2624099 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2624098 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1313553455 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 264796 # Number of bytes of host memory used
|
||||
host_seconds 33.67 # Real time elapsed on the host
|
||||
host_inst_rate 3162077 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3162075 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1582850501 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263736 # Number of bytes of host memory used
|
||||
host_seconds 27.94 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13754477 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.133635 # Nu
|
||||
sim_ticks 133634727000 # Number of ticks simulated
|
||||
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1051168 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1051168 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1590122468 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 273520 # Number of bytes of host memory used
|
||||
host_seconds 84.04 # Real time elapsed on the host
|
||||
host_inst_rate 1560477 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1560477 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2360564466 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 272464 # Number of bytes of host memory used
|
||||
host_seconds 56.61 # Real time elapsed on the host
|
||||
sim_insts 88340673 # Number of instructions simulated
|
||||
sim_ops 88340673 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -110,10 +110,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13754477 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 8748916 9.89% 9.89% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 44395414 50.20% 60.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 44394799 50.20% 60.09% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 41101 0.05% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 60.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 113689 0.13% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 114304 0.13% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 84 0.00% 60.27% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 113640 0.13% 60.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 50 0.00% 60.40% # Class of executed instruction
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.053932 # Number of seconds simulated
|
||||
sim_ticks 53932157000 # Number of ticks simulated
|
||||
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.048960 # Number of seconds simulated
|
||||
sim_ticks 48960011000 # Number of ticks simulated
|
||||
final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1371353 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1946078 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1042965622 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 308436 # Number of bytes of host memory used
|
||||
host_seconds 51.71 # Real time elapsed on the host
|
||||
host_inst_rate 1457592 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1864058 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1006352889 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 314048 # Number of bytes of host memory used
|
||||
host_seconds 48.65 # Real time elapsed on the host
|
||||
sim_insts 70913181 # Number of instructions simulated
|
||||
sim_ops 100632428 # Number of ops (including micro ops) simulated
|
||||
sim_ops 90688136 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
|
||||
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 312580272 # Nu
|
||||
system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 27156252 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 105301320 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 5795805126 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1976063093 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7771868220 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 5795805126 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 5795805126 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1458502967 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1458502967 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 5795805126 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3434566060 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9230371187 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9230371187 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10167763810 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 497813828 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 107864315 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 97920023 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70913181 # Number of instructions committed
|
||||
system.cpu.committedOps 100632428 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses
|
||||
system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 91472780 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 81528488 # number of integer instructions
|
||||
system.cpu.num_fp_insts 56 # number of float instructions
|
||||
system.cpu.num_int_register_reads 452305352 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 141479310 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 47862847 # number of memory refs
|
||||
system.cpu.num_load_insts 27307108 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 43422001 # number of memory refs
|
||||
system.cpu.num_load_insts 22866262 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 107864315 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 97920023 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13741485 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 100634375 # Class of executed instruction
|
||||
system.cpu.op_class::total 90690083 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.132689 # Number of seconds simulated
|
||||
sim_ticks 132689045000 # Number of ticks simulated
|
||||
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.127294 # Number of seconds simulated
|
||||
sim_ticks 127293983000 # Number of ticks simulated
|
||||
final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 682193 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 967367 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1286269606 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318200 # Number of bytes of host memory used
|
||||
host_seconds 103.16 # Real time elapsed on the host
|
||||
host_inst_rate 875914 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1118296 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1584379759 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 323804 # Number of bytes of host memory used
|
||||
host_seconds 80.34 # Real time elapsed on the host
|
||||
sim_insts 70373628 # Number of instructions simulated
|
||||
sim_ops 99791654 # Number of ops (including micro ops) simulated
|
||||
sim_ops 89847362 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
|
||||
@@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 123820 # Nu
|
||||
system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 1925464 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 59722187 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 61647651 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 1925464 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 1925464 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 40471887 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 40471887 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 40471887 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 1925464 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 59722187 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 102119538 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 102119538 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 106447639 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 25532 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 25532 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 83909 # Transaction distribution
|
||||
@@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 13550144 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 882993000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.9 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -138,78 +138,80 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
||||
system.cpu.numCycles 265378090 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 254587966 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 70373628 # Number of instructions committed
|
||||
system.cpu.committedOps 99791654 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses
|
||||
system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3311620 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 91472780 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 9253644 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 81528488 # number of integer instructions
|
||||
system.cpu.num_fp_insts 56 # number of float instructions
|
||||
system.cpu.num_int_register_reads 533671029 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 96252285 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 141328474 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 36 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 20 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 47862847 # number of memory refs
|
||||
system.cpu.num_load_insts 27307108 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 43422001 # number of memory refs
|
||||
system.cpu.num_load_insts 22866262 # Number of load instructions
|
||||
system.cpu.num_store_insts 20555739 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 265378090 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 254587966 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 13741485 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 52691402 52.36% 52.36% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 80119 0.08% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.44% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27307108 27.13% 79.57% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20555739 20.43% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 7 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 52.12% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 100634375 # Class of executed instruction
|
||||
system.cpu.op_class::total 90690083 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 16890 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1736.497265 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1755 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses
|
||||
@@ -225,12 +227,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n
|
||||
system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 18908 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 413722000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 413722000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 413722000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 413722000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 413722000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 413722000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses
|
||||
@@ -243,12 +245,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242
|
||||
system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21880.791199 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21880.791199 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21880.791199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21880.791199 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21880.791199 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -263,44 +265,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908
|
||||
system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 375906000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 375906000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 375906000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 375906000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 375906000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 375906000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19880.791199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19880.791199 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 94693 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30368.194893 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27745.868937 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1154.037281 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1468.288674 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10156 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19788 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 616 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses
|
||||
@@ -328,17 +330,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 127812 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 207838000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1126741000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1334579000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5318574000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5318574000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 207838000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6445315000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6653153000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 207838000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6445315000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6653153000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses)
|
||||
@@ -363,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52063.627255 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52309.238626 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52270.836597 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.136879 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.136879 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52054.212437 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52063.627255 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.908900 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52054.212437 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -395,17 +397,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159934000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868261000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028195000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091214000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091214000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159934000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4959475000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5119409000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159934000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4959475000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5119409000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses
|
||||
@@ -417,90 +419,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40063.627255 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40309.238626 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40270.836597 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.136879 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.136879 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40063.627255 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 155902 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4076.954355 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 46862074 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 292.891624 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 443 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 94204142 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 94204142 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 42576328 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 159998 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 177384 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 123744 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 123744 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 42629968 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 42629968 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 42753712 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 42753712 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -511,40 +521,54 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 128239 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23858 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 23858 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 136140 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.192801 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.192801 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 148145463 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 154424267 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.913189 # Nu
|
||||
sim_ticks 913189263000 # Number of ticks simulated
|
||||
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2693565 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2693565 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1351665756 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 256712 # Number of bytes of host memory used
|
||||
host_seconds 675.60 # Real time elapsed on the host
|
||||
host_inst_rate 3321406 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3321406 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1666724755 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 255644 # Number of bytes of host memory used
|
||||
host_seconds 547.89 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 2.623386 # Nu
|
||||
sim_ticks 2623386226000 # Number of ticks simulated
|
||||
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1099630 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1099630 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1585220760 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265440 # Number of bytes of host memory used
|
||||
host_seconds 1654.90 # Real time elapsed on the host
|
||||
host_inst_rate 1619868 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1619868 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2335193556 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 265412 # Number of bytes of host memory used
|
||||
host_seconds 1123.41 # Real time elapsed on the host
|
||||
sim_insts 1819780127 # Number of instructions simulated
|
||||
sim_ops 1819780127 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -110,10 +110,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 214632552 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 83736345 4.58% 4.58% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1130719228 61.91% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 166 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1129914150 61.87% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 75 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 66.45% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 805244 0.04% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 13 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 100 0.00% 66.50% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 11 0.00% 66.50% # Class of executed instruction
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.861538 # Number of seconds simulated
|
||||
sim_ticks 861538200000 # Number of ticks simulated
|
||||
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.832017 # Number of seconds simulated
|
||||
sim_ticks 832017490000 # Number of ticks simulated
|
||||
final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1785934 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1992340 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 996171702 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 301680 # Number of bytes of host memory used
|
||||
host_seconds 864.85 # Real time elapsed on the host
|
||||
host_inst_rate 1782051 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 959946236 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306272 # Number of bytes of host memory used
|
||||
host_seconds 866.73 # Real time elapsed on the host
|
||||
sim_insts 1544563041 # Number of instructions simulated
|
||||
sim_ops 1723073853 # Number of ops (including micro ops) simulated
|
||||
sim_ops 1664032433 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
|
||||
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 6178262356 # Nu
|
||||
system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9731209155 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 10076480987 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 8383808419 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 1723076401 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 1664034981 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1544563041 # Number of instructions committed
|
||||
system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
|
||||
system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1536941842 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1477900422 # number of integer instructions
|
||||
system.cpu.num_fp_insts 36 # number of float instructions
|
||||
system.cpu.num_int_register_reads 7861285293 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 660773815 # number of memory refs
|
||||
system.cpu.num_load_insts 485926769 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 633153380 # number of memory refs
|
||||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 1723076401 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 1664034981 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462426 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1723073900 # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032480 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.391205 # Number of seconds simulated
|
||||
sim_ticks 2391205115000 # Number of ticks simulated
|
||||
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.363671 # Number of seconds simulated
|
||||
sim_ticks 2363670998000 # Number of ticks simulated
|
||||
final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 867002 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 967582 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1347305237 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 310408 # Number of bytes of host memory used
|
||||
host_seconds 1774.81 # Real time elapsed on the host
|
||||
host_inst_rate 1066052 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1637550718 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 316024 # Number of bytes of host memory used
|
||||
host_seconds 1443.42 # Real time elapsed on the host
|
||||
sim_insts 1538759601 # Number of instructions simulated
|
||||
sim_ops 1717270334 # Number of ops (including micro ops) simulated
|
||||
sim_ops 1658228914 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
|
||||
@@ -25,18 +25,18 @@ system.physmem.num_reads::cpu.data 1958158 # Nu
|
||||
system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 79651138 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 80578984 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
|
||||
system.membus.trans_dist::Writeback 1017198 # Transaction distribution
|
||||
@@ -48,9 +48,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1
|
||||
system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 190462208 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -138,73 +138,75 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 46 # Number of system calls
|
||||
system.cpu.numCycles 4782410230 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 4727341996 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 1538759601 # Number of instructions committed
|
||||
system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
|
||||
system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 27330256 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1536941842 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 1477900422 # number of integer instructions
|
||||
system.cpu.num_fp_insts 36 # number of float instructions
|
||||
system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 660773815 # number of memory refs
|
||||
system.cpu.num_load_insts 485926769 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 633153380 # number of memory refs
|
||||
system.cpu.num_load_insts 458306334 # Number of load instructions
|
||||
system.cpu.num_store_insts 174847046 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 4782410230 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 4727341996 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 213462426 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 1723073900 # Class of executed instruction
|
||||
system.cpu.op_class::total 1664032480 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 7 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
|
||||
@@ -224,12 +226,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n
|
||||
system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 638 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
|
||||
@@ -242,12 +244,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000
|
||||
system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -262,44 +264,44 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638
|
||||
system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 1926075 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses
|
||||
@@ -327,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
|
||||
@@ -362,17 +364,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -394,17 +396,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
|
||||
@@ -416,92 +418,98 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 9111140 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -512,40 +520,48 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 3697418 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.051523 # Nu
|
||||
sim_ticks 51522973500 # Number of ticks simulated
|
||||
final_tick 51522973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 192794 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 192794 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 108084557 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 244692 # Number of bytes of host memory used
|
||||
host_seconds 476.69 # Real time elapsed on the host
|
||||
host_inst_rate 335661 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 335661 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 188179142 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 271092 # Number of bytes of host memory used
|
||||
host_seconds 273.80 # Real time elapsed on the host
|
||||
sim_insts 91903089 # Number of instructions simulated
|
||||
sim_ops 91903089 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 30 3.09% 85.57% # By
|
||||
system.physmem.bytesPerActivate::896-1023 24 2.47% 88.04% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::1024-1151 116 11.96% 100.00% # Bytes accessed per row activation
|
||||
system.physmem.bytesPerActivate::total 970 # Bytes accessed per row activation
|
||||
system.physmem.totQLat 35128750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 134766250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totQLat 35079750 # Total ticks spent queuing
|
||||
system.physmem.totMemAccLat 134717250 # Total ticks spent from burst creation until serviced by the DRAM
|
||||
system.physmem.totBusLat 26570000 # Total ticks spent in databus transfers
|
||||
system.physmem.avgQLat 6610.60 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgQLat 6601.38 # Average queueing delay per DRAM burst
|
||||
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25360.60 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgMemAccLat 25351.38 # Average memory access latency per DRAM burst
|
||||
system.physmem.avgRdBW 6.60 # Average DRAM read bandwidth in MiByte/s
|
||||
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
||||
system.physmem.avgRdBWSys 6.60 # Average system read bandwidth in MiByte/s
|
||||
@@ -218,10 +218,10 @@ system.physmem.readRowHitRate 81.65 # Ro
|
||||
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
||||
system.physmem.avgGap 9695689.12 # Average gap between requests
|
||||
system.physmem.pageHitRate 81.65 # Row buffer hit rate, read and write combined
|
||||
system.physmem.memoryStateTime::IDLE 48460398500 # Time in different power states
|
||||
system.physmem.memoryStateTime::IDLE 48460480000 # Time in different power states
|
||||
system.physmem.memoryStateTime::REF 1720420000 # Time in different power states
|
||||
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1341071500 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT 1340990000 # Time in different power states
|
||||
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
||||
system.membus.throughput 6600861 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 3595 # Transaction distribution
|
||||
@@ -234,40 +234,40 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 340096 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 340096 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 6106000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 6107000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 49717250 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 49715750 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.branchPred.lookups 11407310 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8177170 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 788660 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6672659 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5348436 # Number of BTB hits
|
||||
system.cpu.branchPred.lookups 11407320 # Number of BP lookups
|
||||
system.cpu.branchPred.condPredicted 8177175 # Number of conditional branches predicted
|
||||
system.cpu.branchPred.condIncorrect 788662 # Number of conditional branches incorrect
|
||||
system.cpu.branchPred.BTBLookups 6672694 # Number of BTB lookups
|
||||
system.cpu.branchPred.BTBHits 5348459 # Number of BTB hits
|
||||
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
||||
system.cpu.branchPred.BTBHitPct 80.154493 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1172954 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.BTBHitPct 80.154417 # BTB Hit Percentage
|
||||
system.cpu.branchPred.usedRAS 1172953 # Number of times the RAS was used to get a target.
|
||||
system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions.
|
||||
system.cpu.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 20390002 # DTB read hits
|
||||
system.cpu.dtb.read_hits 20390003 # DTB read hits
|
||||
system.cpu.dtb.read_misses 46972 # DTB read misses
|
||||
system.cpu.dtb.read_acv 0 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 20436974 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6579989 # DTB write hits
|
||||
system.cpu.dtb.read_accesses 20436975 # DTB read accesses
|
||||
system.cpu.dtb.write_hits 6579991 # DTB write hits
|
||||
system.cpu.dtb.write_misses 273 # DTB write misses
|
||||
system.cpu.dtb.write_acv 0 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 6580262 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26969991 # DTB hits
|
||||
system.cpu.dtb.write_accesses 6580264 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 26969994 # DTB hits
|
||||
system.cpu.dtb.data_misses 47245 # DTB misses
|
||||
system.cpu.dtb.data_acv 0 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 27017236 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22956123 # ITB hits
|
||||
system.cpu.dtb.data_accesses 27017239 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 22956162 # ITB hits
|
||||
system.cpu.itb.fetch_misses 88 # ITB misses
|
||||
system.cpu.itb.fetch_acv 0 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 22956211 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 22956250 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
@@ -286,19 +286,19 @@ system.cpu.numWorkItemsStarted 0 # nu
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 91903089 # Number of instructions committed
|
||||
system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed
|
||||
system.cpu.discardedOps 2250201 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.discardedOps 2250216 # Number of ops (including micro ops) which were discarded before commit
|
||||
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
||||
system.cpu.cpi 1.121246 # CPI: cycles per instruction
|
||||
system.cpu.ipc 0.891865 # IPC: instructions per cycle
|
||||
system.cpu.tickCycles 100852498 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 2193449 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.tickCycles 100852685 # Number of cycles that the object actually ticked
|
||||
system.cpu.idleCycles 2193262 # Total number of cycles that the object has spent stopped
|
||||
system.cpu.icache.tags.replacements 13697 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1640.300459 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22940462 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.tagsinuse 1640.300457 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 22940501 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 15661 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1464.814635 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 1464.817125 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300459 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1640.300457 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.800928 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.800928 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id
|
||||
@@ -308,44 +308,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 670
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 149 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::4 947 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 45927907 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45927907 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22940462 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22940462 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22940462 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22940462 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22940462 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22940462 # number of overall hits
|
||||
system.cpu.icache.tags.tag_accesses 45927985 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 45927985 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 22940501 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 22940501 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 22940501 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 22940501 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 22940501 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 22940501 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 15661 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 15661 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 15661 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 15661 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 15661 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 15661 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 385817000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 385817000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 385817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 385817000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 385817000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 385817000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22956123 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22956123 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22956123 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22956123 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22956123 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22956123 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 385791500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 385791500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 385791500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 385791500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 385791500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 385791500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 22956162 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 22956162 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 22956162 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 22956162 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 22956162 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 22956162 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000682 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.000682 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.000682 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_miss_rate::total 0.000682 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000682 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000682 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24635.527744 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24635.527744 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24635.527744 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24635.527744 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24635.527744 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24633.899496 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 24633.899496 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 24633.899496 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -360,24 +360,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15661
|
||||
system.cpu.icache.demand_mshr_misses::total 15661 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 15661 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 15661 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353131000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 353131000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353131000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 353131000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353131000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 353131000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353105500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 353105500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353105500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 353105500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353105500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 353105500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000682 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000682 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000682 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000682 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22548.432412 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22548.432412 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22548.432412 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22548.432412 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22546.804163 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22546.804163 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 22546.804163 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 22356474 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 16146 # Transaction distribution
|
||||
@@ -400,13 +400,13 @@ system.cpu.toL2Bus.respLayer0.utilization 0.0 # L
|
||||
system.cpu.toL2Bus.respLayer1.occupancy 3734250 # Layer occupancy (ticks)
|
||||
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.580709 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 2477.580697 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 12565 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 3661 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 3.432122 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.790278 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790431 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 17.790277 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2459.790419 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.075067 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.075610 # Average percentage of cache occupancy
|
||||
@@ -437,14 +437,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 5314 #
|
||||
system.cpu.l2cache.demand_misses::total 5314 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 5314 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 5314 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245039250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 245039250 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117228000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 117228000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 362267250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 362267250 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 362267250 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 362267250 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 245013750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 245013750 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 117202000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 117202000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 362215750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 362215750 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 362215750 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 362215750 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 16146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 16146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
|
||||
@@ -463,14 +463,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.297021
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.297021 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.297021 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.297021 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68161.126565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.126565 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68195.462478 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68195.462478 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68172.233722 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68172.233722 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68172.233722 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68154.033380 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 68154.033380 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 68180.337405 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68180.337405 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 68162.542341 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -487,14 +487,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 5314
|
||||
system.cpu.l2cache.demand_mshr_misses::total 5314 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5314 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_misses::total 5314 # number of overall MSHR misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199861250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199861250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95675500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95675500 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295536750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 295536750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295536750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 295536750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 199838750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 199838750 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 95648000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95648000 # number of ReadExReq MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 295486750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency::total 295486750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 295486750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_latency::total 295486750 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.222656 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.222656 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.985100 # mshr miss rate for ReadExReq accesses
|
||||
@@ -503,22 +503,22 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.297021
|
||||
system.cpu.l2cache.demand_mshr_miss_rate::total 0.297021 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.297021 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_miss_rate::total 0.297021 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55594.228095 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55594.228095 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55657.649796 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55657.649796 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55614.744072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55614.744072 # average overall mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55587.969402 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55587.969402 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 55641.652123 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55641.652123 # average ReadExReq mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55605.334964 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 157 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1448.553123 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26545427 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1448.553115 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 26545428 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11903.778924 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 11903.779372 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553123 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.inst 1448.553115 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.inst 0.353651 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.353651 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id
|
||||
@@ -528,16 +528,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 53099944 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53099944 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 20047235 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20047235 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 53099946 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 53099946 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.inst 20047236 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 20047236 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.inst 6498192 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 26545427 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26545427 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 26545427 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26545427 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.inst 26545428 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 26545428 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.inst 26545428 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 26545428 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.inst 2911 # number of WriteReq misses
|
||||
@@ -548,20 +548,20 @@ system.cpu.dcache.overall_misses::cpu.inst 3430 #
|
||||
system.cpu.dcache.overall_misses::total 3430 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.inst 36876750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 36876750 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198662500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 198662500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 235539250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235539250 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 235539250 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235539250 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 20047754 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20047754 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.inst 198611000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 198611000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.inst 235487750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 235487750 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.inst 235487750 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 235487750 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.inst 20047755 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 20047755 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.inst 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 26548857 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26548857 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 26548857 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26548857 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.inst 26548858 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 26548858 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.inst 26548858 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 26548858 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000448 # miss rate for WriteReq accesses
|
||||
@@ -572,12 +572,12 @@ system.cpu.dcache.overall_miss_rate::cpu.inst 0.000129
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 71053.468208 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 71053.468208 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68245.448300 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68245.448300 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 68670.335277 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68670.335277 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 68670.335277 # average overall miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68227.756785 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 68227.756785 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.inst 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 68655.320700 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -606,12 +606,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.inst 2230
|
||||
system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 33572250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 33572250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119233500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 119233500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152805750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 152805750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152805750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 152805750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 119207500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 119207500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 152779750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 152779750 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 152779750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 152779750 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000268 # mshr miss rate for WriteReq accesses
|
||||
@@ -622,12 +622,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.000084
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 69221.134021 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69221.134021 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68328.653295 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68328.653295 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68522.757848 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68522.757848 # average overall mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 68313.753582 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68313.753582 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 68511.098655 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.045952 # Nu
|
||||
sim_ticks 45951567500 # Number of ticks simulated
|
||||
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2663178 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2663177 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1331588953 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 260384 # Number of bytes of host memory used
|
||||
host_seconds 34.51 # Real time elapsed on the host
|
||||
host_inst_rate 3319618 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 3319616 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1659808736 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 259284 # Number of bytes of host memory used
|
||||
host_seconds 27.68 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -96,10 +96,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 10240685 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
|
||||
|
||||
@@ -4,11 +4,11 @@ sim_seconds 0.118729 # Nu
|
||||
sim_ticks 118729316000 # Number of ticks simulated
|
||||
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1199929 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1199929 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1550185026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 269088 # Number of bytes of host memory used
|
||||
host_seconds 76.59 # Real time elapsed on the host
|
||||
host_inst_rate 1742639 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1742639 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2251309988 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268020 # Number of bytes of host memory used
|
||||
host_seconds 52.74 # Real time elapsed on the host
|
||||
sim_insts 91903056 # Number of instructions simulated
|
||||
sim_ops 91903056 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -102,10 +102,10 @@ system.cpu.not_idle_fraction 1 # Pe
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 10240685 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 7723353 8.40% 8.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 51001543 55.49% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 51001454 55.49% 63.90% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 458252 0.50% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 64.40% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2732464 2.97% 67.37% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 2732553 2.97% 67.37% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 104605 0.11% 67.48% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 2333953 2.54% 70.02% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 296445 0.32% 70.35% # Class of executed instruction
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.103107 # Number of seconds simulated
|
||||
sim_ticks 103106766000 # Number of ticks simulated
|
||||
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.099596 # Number of seconds simulated
|
||||
sim_ticks 99596491000 # Number of ticks simulated
|
||||
final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1728223 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1892237 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1034088491 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 304984 # Number of bytes of host memory used
|
||||
host_seconds 99.71 # Real time elapsed on the host
|
||||
host_inst_rate 1821315 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1919960 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1052688537 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 309564 # Number of bytes of host memory used
|
||||
host_seconds 94.61 # Real time elapsed on the host
|
||||
sim_insts 172317409 # Number of instructions simulated
|
||||
sim_ops 188670891 # Number of ops (including micro ops) simulated
|
||||
sim_ops 181650341 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
|
||||
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 759440204 # Nu
|
||||
system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 29622453 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 219482504 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 7365570985 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1072031112 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8437602097 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7365570985 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7365570985 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 438893991 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 438893991 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7365570985 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1510925103 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 8876496088 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 8876496088 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9189347896 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 915226805 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 206213533 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 199192983 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 172317409 # Number of instructions committed
|
||||
system.cpu.committedOps 188670891 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
|
||||
system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 150106218 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 143085668 # number of integer instructions
|
||||
system.cpu.num_fp_insts 1752310 # number of float instructions
|
||||
system.cpu.num_int_register_reads 815315678 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 241970171 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 42494119 # number of memory refs
|
||||
system.cpu.num_load_insts 29849484 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 40540779 # number of memory refs
|
||||
system.cpu.num_load_insts 27896144 # Number of load instructions
|
||||
system.cpu.num_store_insts 12644635 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 206213533 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 199192983 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 40300311 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 188671292 # Class of executed instruction
|
||||
system.cpu.op_class::total 181650742 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.232072 # Number of seconds simulated
|
||||
sim_ticks 232072304000 # Number of ticks simulated
|
||||
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.230173 # Number of seconds simulated
|
||||
sim_ticks 230173357000 # Number of ticks simulated
|
||||
final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 924224 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1012125 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1248159761 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 313696 # Number of bytes of host memory used
|
||||
host_seconds 185.93 # Real time elapsed on the host
|
||||
host_inst_rate 1246866 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1314511 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 1670106565 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 319316 # Number of bytes of host memory used
|
||||
host_seconds 137.82 # Real time elapsed on the host
|
||||
sim_insts 171842483 # Number of instructions simulated
|
||||
sim_ops 188185920 # Number of ops (including micro ops) simulated
|
||||
sim_ops 181165370 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
|
||||
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 110656 # Nu
|
||||
system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 476817 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 475438 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 952255 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 476817 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 476817 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 476817 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 475438 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 952255 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 952255 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 960111 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 2361 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 1092 # Transaction distribution
|
||||
@@ -40,9 +40,9 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 220992 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 3453000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
@@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 400 # Number of system calls
|
||||
system.cpu.numCycles 464144608 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 460346714 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 171842483 # Number of instructions committed
|
||||
system.cpu.committedOps 188185920 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses
|
||||
system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 3545028 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 150106218 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 143085668 # number of integer instructions
|
||||
system.cpu.num_fp_insts 1752310 # number of float instructions
|
||||
system.cpu.num_int_register_reads 904571312 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 294073517 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 242291225 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 42494119 # number of memory refs
|
||||
system.cpu.num_load_insts 29849484 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 40540779 # number of memory refs
|
||||
system.cpu.num_load_insts 27896144 # Number of load instructions
|
||||
system.cpu.num_store_insts 12644635 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 464144608 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 460346714 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 40300311 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 144055422 76.35% 76.35% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 908940 0.48% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 76.83% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 32754 0.02% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 76.85% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 154829 0.08% 76.93% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.06% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.10% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 437591 0.23% 77.33% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.44% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.48% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 29849484 15.82% 93.30% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 12644635 6.70% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 77.01% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 32754 0.02% 77.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 77.03% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 154829 0.09% 77.12% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 238880 0.13% 77.25% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 76016 0.04% 77.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 437591 0.24% 77.53% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 188671292 # Class of executed instruction
|
||||
system.cpu.op_class::total 181650742 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1506 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 1147.986161 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
||||
@@ -218,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n
|
||||
system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 3051 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112281000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 112281000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 112281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 112281000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 112281000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 112281000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses
|
||||
@@ -236,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016
|
||||
system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36801.376598 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36801.376598 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36801.376598 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -256,34 +258,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051
|
||||
system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34801.376598 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.655740 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.038044 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.032828 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.584868 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
|
||||
@@ -321,17 +323,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 3453 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89908000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32864000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 122772000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56784000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 56784000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 89908000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 89648000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 179556000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 89908000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 89648000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 179556000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses)
|
||||
@@ -356,17 +358,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -421,14 +423,14 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 40 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 1363.611259 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 42007358 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 23480.915595 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
|
||||
@@ -436,64 +438,72 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 67
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 84020083 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 84020083 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
|
||||
system.cpu.dcache.demand_hits::cpu.data 40117350 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 40117350 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 40117812 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 40117812 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 688 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 688 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1789 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 40119138 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 40119138 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 40119601 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 40119601 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000025 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.000025 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -504,40 +514,48 @@ system.cpu.dcache.fast_writes 0 # nu
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 1339169 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 1350217 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,70 +1,73 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.870336 # Number of seconds simulated
|
||||
sim_ticks 1870335522500 # Number of ticks simulated
|
||||
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 1.870335 # Number of seconds simulated
|
||||
sim_ticks 1870335131500 # Number of ticks simulated
|
||||
final_tick 1870335131500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2258331 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2258329 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 66881420828 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 346748 # Number of bytes of host memory used
|
||||
host_seconds 27.97 # Real time elapsed on the host
|
||||
sim_insts 63154034 # Number of instructions simulated
|
||||
sim_ops 63154034 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1824221 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1824220 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 54024573563 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 318368 # Number of bytes of host memory used
|
||||
host_seconds 34.62 # Real time elapsed on the host
|
||||
sim_insts 63154606 # Number of instructions simulated
|
||||
sim_ops 63154606 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66693056 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2649600 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.inst 761088 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu0.data 66705472 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.inst 110976 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 668672 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 70883520 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 761216 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_read::cpu1.data 674112 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 68252608 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu0.inst 761088 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu1.inst 110976 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 872192 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7861504 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7861504 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 11894 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1042079 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41400 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_inst_read::total 872064 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 5204096 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7863424 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu0.inst 11892 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu0.data 1042273 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.inst 1734 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu1.data 10448 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1107555 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 122836 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122836 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 406994 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35658338 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1416644 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu1.data 10533 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1066447 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 81314 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 122866 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu0.inst 406926 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu0.data 35664984 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 513 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.inst 59335 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 357514 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37898826 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 406994 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu1.data 360423 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 36492181 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu0.inst 406926 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu1.inst 59335 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 466329 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4203259 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4203259 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4203259 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 406994 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35658338 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1416644 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 466261 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2782440 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::tsunami.ide 1421846 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4204286 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2782440 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.inst 406926 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu0.data 35664984 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1422359 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.inst 59335 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu1.data 357514 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 42160248 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 78853810 # Total data (bytes)
|
||||
system.physmem.bw_total::cpu1.data 360423 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 40696467 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 40739369 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 76196274 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.l2c.tags.replacements 1000626 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65381.922680 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2464737 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1065768 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.312639 # Average number of references to valid blocks.
|
||||
system.l2c.tags.replacements 1000624 # number of replacements
|
||||
system.l2c.tags.tagsinuse 65381.923240 # Cycle average of tags in use
|
||||
system.l2c.tags.total_refs 2464778 # Total number of references to valid blocks.
|
||||
system.l2c.tags.sampled_refs 1065766 # Sample count of references to valid blocks.
|
||||
system.l2c.tags.avg_refs 2.312682 # Average number of references to valid blocks.
|
||||
system.l2c.tags.warmup_cycle 838081000 # Cycle when the warmup percentage was hit.
|
||||
system.l2c.tags.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4134.601551 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 174.423287 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 19.958294 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::writebacks 56158.686870 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.inst 4894.230886 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu0.data 4134.623273 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.inst 174.423683 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_blocks::cpu1.data 19.958527 # Average occupied blocks per requestor
|
||||
system.l2c.tags.occ_percent::writebacks 0.856914 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.inst 0.074680 # Average percentage of cache occupancy
|
||||
system.l2c.tags.occ_percent::cpu0.data 0.063089 # Average percentage of cache occupancy
|
||||
@@ -75,42 +78,42 @@ system.l2c.tags.occ_task_id_blocks::1024 65142 # Oc
|
||||
system.l2c.tags.age_task_id_blocks_1024::0 769 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::1 3264 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::2 6912 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 6232 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 47965 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::3 6213 # Occupied blocks per task id
|
||||
system.l2c.tags.age_task_id_blocks_1024::4 47984 # Occupied blocks per task id
|
||||
system.l2c.tags.occ_task_id_percent::1024 0.993988 # Percentage of cache occupancy per task id
|
||||
system.l2c.tags.tag_accesses 32109442 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 32109442 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 816653 # number of Writeback hits
|
||||
system.l2c.tags.tag_accesses 32109770 # Number of tag accesses
|
||||
system.l2c.tags.data_accesses 32109770 # Number of data accesses
|
||||
system.l2c.ReadReq_hits::cpu0.inst 873092 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu0.data 763091 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.inst 101902 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::cpu1.data 36740 # number of ReadReq hits
|
||||
system.l2c.ReadReq_hits::total 1774825 # number of ReadReq hits
|
||||
system.l2c.Writeback_hits::writebacks 816663 # number of Writeback hits
|
||||
system.l2c.Writeback_hits::total 816663 # number of Writeback hits
|
||||
system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
|
||||
system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
|
||||
system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits
|
||||
system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 929311 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 51019 # number of overall hits
|
||||
system.l2c.overall_hits::total 1955312 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses
|
||||
system.l2c.ReadExReq_hits::cpu0.data 166232 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::cpu1.data 14288 # number of ReadExReq hits
|
||||
system.l2c.ReadExReq_hits::total 180520 # number of ReadExReq hits
|
||||
system.l2c.demand_hits::cpu0.inst 873092 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu0.data 929323 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.inst 101902 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::cpu1.data 51028 # number of demand (read+write) hits
|
||||
system.l2c.demand_hits::total 1955345 # number of demand (read+write) hits
|
||||
system.l2c.overall_hits::cpu0.inst 873092 # number of overall hits
|
||||
system.l2c.overall_hits::cpu0.data 929323 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.inst 101902 # number of overall hits
|
||||
system.l2c.overall_hits::cpu1.data 51028 # number of overall hits
|
||||
system.l2c.overall_hits::total 1955345 # number of overall hits
|
||||
system.l2c.ReadReq_misses::cpu0.inst 11892 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::cpu1.data 908 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 941297 # number of ReadReq misses
|
||||
system.l2c.ReadReq_misses::total 941295 # number of ReadReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu0.data 2442 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::cpu1.data 570 # number of UpgradeReq misses
|
||||
system.l2c.UpgradeReq_misses::total 3012 # number of UpgradeReq misses
|
||||
@@ -120,66 +123,66 @@ system.l2c.SCUpgradeReq_misses::total 165 # nu
|
||||
system.l2c.ReadExReq_misses::cpu0.data 115706 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::cpu1.data 9662 # number of ReadExReq misses
|
||||
system.l2c.ReadExReq_misses::total 125368 # number of ReadExReq misses
|
||||
system.l2c.demand_misses::cpu0.inst 11894 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.inst 11892 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu0.data 1042467 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.inst 1734 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::cpu1.data 10570 # number of demand (read+write) misses
|
||||
system.l2c.demand_misses::total 1066665 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11894 # number of overall misses
|
||||
system.l2c.demand_misses::total 1066663 # number of demand (read+write) misses
|
||||
system.l2c.overall_misses::cpu0.inst 11892 # number of overall misses
|
||||
system.l2c.overall_misses::cpu0.data 1042467 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.inst 1734 # number of overall misses
|
||||
system.l2c.overall_misses::cpu1.data 10570 # number of overall misses
|
||||
system.l2c.overall_misses::total 1066665 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.overall_misses::total 1066663 # number of overall misses
|
||||
system.l2c.ReadReq_accesses::cpu0.inst 884984 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu0.data 1689852 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.inst 103636 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::cpu1.data 37648 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.ReadReq_accesses::total 2716120 # number of ReadReq accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::writebacks 816663 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.Writeback_accesses::total 816663 # number of Writeback accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadExReq_accesses::cpu0.data 281938 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::cpu1.data 23950 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.ReadExReq_accesses::total 305888 # number of ReadExReq accesses(hits+misses)
|
||||
system.l2c.demand_accesses::cpu0.inst 884984 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu0.data 1971790 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.inst 103636 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::cpu1.data 61598 # number of demand (read+write) accesses
|
||||
system.l2c.demand_accesses::total 3022008 # number of demand (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.inst 884984 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu0.data 1971790 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.inst 103636 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::cpu1.data 61598 # number of overall (read+write) accesses
|
||||
system.l2c.overall_accesses::total 3022008 # number of overall (read+write) accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.inst 0.013438 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu0.data 0.548427 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.inst 0.016732 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::cpu1.data 0.024118 # miss rate for ReadReq accesses
|
||||
system.l2c.ReadReq_miss_rate::total 0.346559 # miss rate for ReadReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses
|
||||
system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu0.data 0.410395 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::cpu1.data 0.403424 # miss rate for ReadExReq accesses
|
||||
system.l2c.ReadExReq_miss_rate::total 0.409849 # miss rate for ReadExReq accesses
|
||||
system.l2c.demand_miss_rate::cpu0.inst 0.013438 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu0.data 0.528691 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.inst 0.016732 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::cpu1.data 0.171596 # miss rate for demand accesses
|
||||
system.l2c.demand_miss_rate::total 0.352965 # miss rate for demand accesses
|
||||
system.l2c.overall_miss_rate::cpu0.inst 0.013438 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu0.data 0.528691 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.inst 0.016732 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::cpu1.data 0.171596 # miss rate for overall accesses
|
||||
system.l2c.overall_miss_rate::total 0.352965 # miss rate for overall accesses
|
||||
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -188,16 +191,16 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av
|
||||
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.l2c.fast_writes 0 # number of fast writes performed
|
||||
system.l2c.cache_copies 0 # number of cache copies performed
|
||||
system.l2c.writebacks::writebacks 81316 # number of writebacks
|
||||
system.l2c.writebacks::total 81316 # number of writebacks
|
||||
system.l2c.writebacks::writebacks 81314 # number of writebacks
|
||||
system.l2c.writebacks::total 81314 # number of writebacks
|
||||
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.iocache.tags.replacements 41695 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.435437 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.435433 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41711 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685787165017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 0.435437 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 0.435433 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.027215 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.027215 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
@@ -205,26 +208,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 375543 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 375543 # Number of data accesses
|
||||
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
|
||||
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
|
||||
system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 175 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41727 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41727 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41727 # number of overall misses
|
||||
system.iocache.overall_misses::total 41727 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 175 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 175 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 175 # number of overall misses
|
||||
system.iocache.overall_misses::total 175 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 175 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41727 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41727 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41727 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41727 # number of overall (read+write) accesses
|
||||
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 175 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 175 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 175 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 175 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
@@ -235,10 +236,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.fast_writes 41552 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
||||
system.iocache.writebacks::total 41520 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
@@ -256,22 +255,22 @@ system.cpu0.dtb.fetch_hits 0 # IT
|
||||
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu0.dtb.read_hits 9154530 # DTB read hits
|
||||
system.cpu0.dtb.read_hits 9154569 # DTB read hits
|
||||
system.cpu0.dtb.read_misses 7079 # DTB read misses
|
||||
system.cpu0.dtb.read_acv 152 # DTB read access violations
|
||||
system.cpu0.dtb.read_accesses 508987 # DTB read accesses
|
||||
system.cpu0.dtb.write_hits 5936899 # DTB write hits
|
||||
system.cpu0.dtb.write_hits 5936918 # DTB write hits
|
||||
system.cpu0.dtb.write_misses 726 # DTB write misses
|
||||
system.cpu0.dtb.write_acv 99 # DTB write access violations
|
||||
system.cpu0.dtb.write_accesses 189050 # DTB write accesses
|
||||
system.cpu0.dtb.data_hits 15091429 # DTB hits
|
||||
system.cpu0.dtb.data_hits 15091487 # DTB hits
|
||||
system.cpu0.dtb.data_misses 7805 # DTB misses
|
||||
system.cpu0.dtb.data_acv 251 # DTB access violations
|
||||
system.cpu0.dtb.data_accesses 698037 # DTB accesses
|
||||
system.cpu0.itb.fetch_hits 3855556 # ITB hits
|
||||
system.cpu0.itb.fetch_hits 3855534 # ITB hits
|
||||
system.cpu0.itb.fetch_misses 3485 # ITB misses
|
||||
system.cpu0.itb.fetch_acv 127 # ITB acv
|
||||
system.cpu0.itb.fetch_accesses 3859041 # ITB accesses
|
||||
system.cpu0.itb.fetch_accesses 3859019 # ITB accesses
|
||||
system.cpu0.itb.read_hits 0 # DTB read hits
|
||||
system.cpu0.itb.read_misses 0 # DTB read misses
|
||||
system.cpu0.itb.read_acv 0 # DTB read access violations
|
||||
@@ -284,34 +283,34 @@ system.cpu0.itb.data_hits 0 # DT
|
||||
system.cpu0.itb.data_misses 0 # DTB misses
|
||||
system.cpu0.itb.data_acv 0 # DTB access violations
|
||||
system.cpu0.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu0.numCycles 3740671046 # number of cpu cycles simulated
|
||||
system.cpu0.numCycles 3740670264 # number of cpu cycles simulated
|
||||
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu0.committedInsts 57222076 # Number of instructions committed
|
||||
system.cpu0.committedOps 57222076 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 53249924 # Number of integer alu accesses
|
||||
system.cpu0.committedInsts 57222643 # Number of instructions committed
|
||||
system.cpu0.committedOps 57222643 # Number of ops (including micro ops) committed
|
||||
system.cpu0.num_int_alu_accesses 53250480 # Number of integer alu accesses
|
||||
system.cpu0.num_fp_alu_accesses 299810 # Number of float alu accesses
|
||||
system.cpu0.num_func_calls 1399585 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 6808233 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 53249924 # number of integer instructions
|
||||
system.cpu0.num_func_calls 1399593 # number of times a function call or return occured
|
||||
system.cpu0.num_conditional_control_insts 6808341 # number of instructions that are conditional controls
|
||||
system.cpu0.num_int_insts 53250480 # number of integer instructions
|
||||
system.cpu0.num_fp_insts 299810 # number of float instructions
|
||||
system.cpu0.num_int_register_reads 73318596 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 39827534 # number of times the integer registers were written
|
||||
system.cpu0.num_int_register_reads 73319539 # number of times the integer registers were read
|
||||
system.cpu0.num_int_register_writes 39827957 # number of times the integer registers were written
|
||||
system.cpu0.num_fp_register_reads 147724 # number of times the floating registers were read
|
||||
system.cpu0.num_fp_register_writes 150835 # number of times the floating registers were written
|
||||
system.cpu0.num_mem_refs 15135515 # number of memory refs
|
||||
system.cpu0.num_load_insts 9184477 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5951038 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3683437200.584730 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57233845.415270 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984700 # Percentage of idle cycles
|
||||
system.cpu0.Branches 8650704 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 3102513 5.42% 5.42% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 37823162 66.09% 71.51% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 59490 0.10% 71.61% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 18488 0.03% 71.65% # Class of executed instruction
|
||||
system.cpu0.num_mem_refs 15135573 # number of memory refs
|
||||
system.cpu0.num_load_insts 9184516 # Number of load instructions
|
||||
system.cpu0.num_store_insts 5951057 # Number of store instructions
|
||||
system.cpu0.num_idle_cycles 3683435851.584730 # Number of idle cycles
|
||||
system.cpu0.num_busy_cycles 57234412.415270 # Number of busy cycles
|
||||
system.cpu0.not_idle_fraction 0.015301 # Percentage of non-idle cycles
|
||||
system.cpu0.idle_fraction 0.984699 # Percentage of idle cycles
|
||||
system.cpu0.Branches 8650822 # Number of branches fetched
|
||||
system.cpu0.op_class::No_OpClass 3102524 5.42% 5.42% # Class of executed instruction
|
||||
system.cpu0.op_class::IntAlu 37811313 66.07% 71.49% # Class of executed instruction
|
||||
system.cpu0.op_class::IntMult 59497 0.10% 71.59% # Class of executed instruction
|
||||
system.cpu0.op_class::IntDiv 0 0.00% 71.59% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatAdd 30844 0.05% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCmp 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatCvt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::FloatMult 0 0.00% 71.65% # Class of executed instruction
|
||||
@@ -337,38 +336,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.65% # Cl
|
||||
system.cpu0.op_class::SimdFloatMult 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.65% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 9401052 16.43% 88.08% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 5956984 10.41% 98.49% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 866222 1.51% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::MemRead 9401091 16.43% 88.08% # Class of executed instruction
|
||||
system.cpu0.op_class::MemWrite 5957003 10.41% 98.49% # Class of executed instruction
|
||||
system.cpu0.op_class::IprAccess 866206 1.51% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu0.op_class::total 57230132 # Class of executed instruction
|
||||
system.cpu0.op_class::total 57230699 # Class of executed instruction
|
||||
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu0.kern.inst.quiesce 6283 # number of quiesce instructions executed
|
||||
system.cpu0.kern.inst.hwrei 197120 # number of hwrei instructions executed
|
||||
system.cpu0.kern.inst.hwrei 197118 # number of hwrei instructions executed
|
||||
system.cpu0.kern.ipl_count::0 71004 40.60% 40.60% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::21 243 0.14% 40.74% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::22 1908 1.09% 41.83% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::30 8 0.00% 41.84% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::31 101705 58.16% 100.00% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::total 174868 # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::31 101703 58.16% 100.00% # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_count::total 174866 # number of times we switched to this ipl
|
||||
system.cpu0.kern.ipl_good::0 69637 49.24% 49.24% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::21 243 0.17% 49.41% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::22 1908 1.35% 50.76% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::30 8 0.01% 50.77% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::31 69629 49.23% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_good::total 141425 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu0.kern.ipl_ticks::0 1852989766500 99.07% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::0 1852989089000 99.07% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::21 20110000 0.00% 99.07% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::22 82044000 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::30 949500 0.00% 99.08% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::31 17242445000 0.92% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::total 1870335315000 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::31 17242731500 0.92% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_ticks::total 1870334924000 # number of cycles we spent at this ipl
|
||||
system.cpu0.kern.ipl_used::0 0.980748 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::31 0.684617 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::total 0.808753 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::31 0.684631 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.ipl_used::total 0.808762 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu0.kern.syscall::2 6 2.65% 2.65% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::3 19 8.41% 11.06% # number of syscalls executed
|
||||
system.cpu0.kern.syscall::4 2 0.88% 11.95% # number of syscalls executed
|
||||
@@ -408,7 +407,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.06% # nu
|
||||
system.cpu0.kern.callpal::swpctx 3762 2.05% 2.11% # number of callpals executed
|
||||
system.cpu0.kern.callpal::tbi 38 0.02% 2.14% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrent 7 0.00% 2.14% # number of callpals executed
|
||||
system.cpu0.kern.callpal::swpipl 168035 91.68% 93.82% # number of callpals executed
|
||||
system.cpu0.kern.callpal::swpipl 168033 91.68% 93.82% # number of callpals executed
|
||||
system.cpu0.kern.callpal::rdps 6150 3.36% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.17% # number of callpals executed
|
||||
system.cpu0.kern.callpal::wrusp 3 0.00% 97.17% # number of callpals executed
|
||||
@@ -417,19 +416,19 @@ system.cpu0.kern.callpal::whami 2 0.00% 97.18% # nu
|
||||
system.cpu0.kern.callpal::rti 4673 2.55% 99.73% # number of callpals executed
|
||||
system.cpu0.kern.callpal::callsys 357 0.19% 99.92% # number of callpals executed
|
||||
system.cpu0.kern.callpal::imb 142 0.08% 100.00% # number of callpals executed
|
||||
system.cpu0.kern.callpal::total 183291 # number of callpals executed
|
||||
system.cpu0.kern.callpal::total 183289 # number of callpals executed
|
||||
system.cpu0.kern.mode_switch::kernel 7091 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::user 1158 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::user 1156 # number of protection mode switches
|
||||
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
||||
system.cpu0.kern.mode_good::kernel 1157
|
||||
system.cpu0.kern.mode_good::user 1158
|
||||
system.cpu0.kern.mode_good::kernel 1155
|
||||
system.cpu0.kern.mode_good::user 1156
|
||||
system.cpu0.kern.mode_good::idle 0
|
||||
system.cpu0.kern.mode_switch_good::kernel 0.163165 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::kernel 0.162883 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_switch_good::total 0.280640 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks::kernel 1869378305000 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::user 957009000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_switch_good::total 0.280223 # fraction of useful protection mode switches
|
||||
system.cpu0.kern.mode_ticks::kernel 1869377924000 99.95% 99.95% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::user 956999000 0.05% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu0.kern.swap_context 3763 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
@@ -463,18 +462,18 @@ system.tsunami.ethernet.totalRxOrn 0 # to
|
||||
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
||||
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.toL2Bus.throughput 131930255 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 246743474 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 10368 # Total snoop data (bytes)
|
||||
system.toL2Bus.throughput 133353257 # Throughput (bytes/s)
|
||||
system.toL2Bus.data_through_bus 246745714 # Total data (bytes)
|
||||
system.toL2Bus.snoop_data_through_bus 2669568 # Total snoop data (bytes)
|
||||
system.iobus.throughput 1460501 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 2731626 # Total data (bytes)
|
||||
system.cpu0.icache.tags.replacements 884404 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.244754 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 56345132 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 884916 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 63.672859 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.replacements 884408 # number of replacements
|
||||
system.cpu0.icache.tags.tagsinuse 511.244752 # Cycle average of tags in use
|
||||
system.cpu0.icache.tags.total_refs 56345695 # Total number of references to valid blocks.
|
||||
system.cpu0.icache.tags.sampled_refs 884920 # Sample count of references to valid blocks.
|
||||
system.cpu0.icache.tags.avg_refs 63.673208 # Average number of references to valid blocks.
|
||||
system.cpu0.icache.tags.warmup_cycle 9786576500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244754 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.244752 # Average occupied blocks per requestor
|
||||
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998525 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_percent::total 0.998525 # Average percentage of cache occupancy
|
||||
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
@@ -482,26 +481,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 59
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.age_task_id_blocks_1024::2 345 # Occupied blocks per task id
|
||||
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.icache.tags.tag_accesses 58115132 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 58115132 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 56345132 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 56345132 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 56345132 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 56345132 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 56345132 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 56345132 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 885000 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 885000 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 885000 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 885000 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 885000 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 885000 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 57230132 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 57230132 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 57230132 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 57230132 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 57230132 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.tags.tag_accesses 58115703 # Number of tag accesses
|
||||
system.cpu0.icache.tags.data_accesses 58115703 # Number of data accesses
|
||||
system.cpu0.icache.ReadReq_hits::cpu0.inst 56345695 # number of ReadReq hits
|
||||
system.cpu0.icache.ReadReq_hits::total 56345695 # number of ReadReq hits
|
||||
system.cpu0.icache.demand_hits::cpu0.inst 56345695 # number of demand (read+write) hits
|
||||
system.cpu0.icache.demand_hits::total 56345695 # number of demand (read+write) hits
|
||||
system.cpu0.icache.overall_hits::cpu0.inst 56345695 # number of overall hits
|
||||
system.cpu0.icache.overall_hits::total 56345695 # number of overall hits
|
||||
system.cpu0.icache.ReadReq_misses::cpu0.inst 885004 # number of ReadReq misses
|
||||
system.cpu0.icache.ReadReq_misses::total 885004 # number of ReadReq misses
|
||||
system.cpu0.icache.demand_misses::cpu0.inst 885004 # number of demand (read+write) misses
|
||||
system.cpu0.icache.demand_misses::total 885004 # number of demand (read+write) misses
|
||||
system.cpu0.icache.overall_misses::cpu0.inst 885004 # number of overall misses
|
||||
system.cpu0.icache.overall_misses::total 885004 # number of overall misses
|
||||
system.cpu0.icache.ReadReq_accesses::cpu0.inst 57230699 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.ReadReq_accesses::total 57230699 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.icache.demand_accesses::cpu0.inst 57230699 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.demand_accesses::total 57230699 # number of demand (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::cpu0.inst 57230699 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.overall_accesses::total 57230699 # number of overall (read+write) accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015464 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.ReadReq_miss_rate::total 0.015464 # miss rate for ReadReq accesses
|
||||
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015464 # miss rate for demand accesses
|
||||
@@ -517,13 +516,13 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu0.dcache.tags.replacements 1978686 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 507.129778 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 13123753 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1979198 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 6.630844 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.replacements 1978697 # number of replacements
|
||||
system.cpu0.dcache.tags.tagsinuse 507.129647 # Cycle average of tags in use
|
||||
system.cpu0.dcache.tags.total_refs 13123800 # Total number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.sampled_refs 1979209 # Sample count of references to valid blocks.
|
||||
system.cpu0.dcache.tags.avg_refs 6.630831 # Average number of references to valid blocks.
|
||||
system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129778 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.129647 # Average occupied blocks per requestor
|
||||
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.990488 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_percent::total 0.990488 # Average percentage of cache occupancy
|
||||
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
@@ -531,44 +530,44 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 443
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
|
||||
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu0.dcache.tags.tag_accesses 62404072 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 62404072 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7298337 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7298337 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5462263 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 5462263 # number of WriteReq hits
|
||||
system.cpu0.dcache.tags.tag_accesses 62404315 # Number of tag accesses
|
||||
system.cpu0.dcache.tags.data_accesses 62404315 # Number of data accesses
|
||||
system.cpu0.dcache.ReadReq_hits::cpu0.data 7298365 # number of ReadReq hits
|
||||
system.cpu0.dcache.ReadReq_hits::total 7298365 # number of ReadReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::cpu0.data 5462282 # number of WriteReq hits
|
||||
system.cpu0.dcache.WriteReq_hits::total 5462282 # number of WriteReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172144 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.LoadLockedReq_hits::total 172144 # number of LoadLockedReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 186624 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.StoreCondReq_hits::total 186624 # number of StoreCondReq hits
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 12760600 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 12760600 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 12760600 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 12760600 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1683332 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1683332 # number of ReadReq misses
|
||||
system.cpu0.dcache.demand_hits::cpu0.data 12760647 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.demand_hits::total 12760647 # number of demand (read+write) hits
|
||||
system.cpu0.dcache.overall_hits::cpu0.data 12760647 # number of overall hits
|
||||
system.cpu0.dcache.overall_hits::total 12760647 # number of overall hits
|
||||
system.cpu0.dcache.ReadReq_misses::cpu0.data 1683343 # number of ReadReq misses
|
||||
system.cpu0.dcache.ReadReq_misses::total 1683343 # number of ReadReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::cpu0.data 285998 # number of WriteReq misses
|
||||
system.cpu0.dcache.WriteReq_misses::total 285998 # number of WriteReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 16153 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.LoadLockedReq_misses::total 16153 # number of LoadLockedReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 714 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.StoreCondReq_misses::total 714 # number of StoreCondReq misses
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1969330 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1969330 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1969330 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1969330 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981669 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 8981669 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748261 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_misses::cpu0.data 1969341 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.demand_misses::total 1969341 # number of demand (read+write) misses
|
||||
system.cpu0.dcache.overall_misses::cpu0.data 1969341 # number of overall misses
|
||||
system.cpu0.dcache.overall_misses::total 1969341 # number of overall misses
|
||||
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8981708 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.ReadReq_accesses::total 8981708 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5748280 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.WriteReq_accesses::total 5748280 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 188297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.LoadLockedReq_accesses::total 188297 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 187338 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 14729930 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 14729930 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 14729930 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 14729930 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::cpu0.data 14729988 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.demand_accesses::total 14729988 # number of demand (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::cpu0.data 14729988 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.overall_accesses::total 14729988 # number of overall (read+write) accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.187419 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.ReadReq_miss_rate::total 0.187419 # miss rate for ReadReq accesses
|
||||
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049754 # miss rate for WriteReq accesses
|
||||
@@ -589,8 +588,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu0.dcache.writebacks::writebacks 775641 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 775641 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::writebacks 775643 # number of writebacks
|
||||
system.cpu0.dcache.writebacks::total 775643 # number of writebacks
|
||||
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
||||
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
||||
@@ -624,34 +623,34 @@ system.cpu1.itb.data_hits 0 # DT
|
||||
system.cpu1.itb.data_misses 0 # DTB misses
|
||||
system.cpu1.itb.data_acv 0 # DTB access violations
|
||||
system.cpu1.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu1.numCycles 3740248881 # number of cpu cycles simulated
|
||||
system.cpu1.numCycles 3740248099 # number of cpu cycles simulated
|
||||
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu1.committedInsts 5931958 # Number of instructions committed
|
||||
system.cpu1.committedOps 5931958 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 5550578 # Number of integer alu accesses
|
||||
system.cpu1.committedInsts 5931963 # Number of instructions committed
|
||||
system.cpu1.committedOps 5931963 # Number of ops (including micro ops) committed
|
||||
system.cpu1.num_int_alu_accesses 5550581 # Number of integer alu accesses
|
||||
system.cpu1.num_fp_alu_accesses 28590 # Number of float alu accesses
|
||||
system.cpu1.num_func_calls 182742 # number of times a function call or return occured
|
||||
system.cpu1.num_conditional_control_insts 577190 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 5550578 # number of integer instructions
|
||||
system.cpu1.num_conditional_control_insts 577192 # number of instructions that are conditional controls
|
||||
system.cpu1.num_int_insts 5550581 # number of integer instructions
|
||||
system.cpu1.num_fp_insts 28590 # number of float instructions
|
||||
system.cpu1.num_int_register_reads 7657288 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 4163275 # number of times the integer registers were written
|
||||
system.cpu1.num_int_register_reads 7657293 # number of times the integer registers were read
|
||||
system.cpu1.num_int_register_writes 4163277 # number of times the integer registers were written
|
||||
system.cpu1.num_fp_register_reads 17889 # number of times the floating registers were read
|
||||
system.cpu1.num_fp_register_writes 17683 # number of times the floating registers were written
|
||||
system.cpu1.num_mem_refs 1926244 # number of memory refs
|
||||
system.cpu1.num_load_insts 1170888 # Number of load instructions
|
||||
system.cpu1.num_store_insts 755356 # Number of store instructions
|
||||
system.cpu1.num_idle_cycles 3734312190.077655 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 5936690.922345 # Number of busy cycles
|
||||
system.cpu1.num_idle_cycles 3734311403.078359 # Number of idle cycles
|
||||
system.cpu1.num_busy_cycles 5936695.921641 # Number of busy cycles
|
||||
system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles
|
||||
system.cpu1.idle_fraction 0.998413 # Percentage of idle cycles
|
||||
system.cpu1.Branches 836747 # Number of branches fetched
|
||||
system.cpu1.Branches 836749 # Number of branches fetched
|
||||
system.cpu1.op_class::No_OpClass 239814 4.04% 4.04% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 3533366 59.53% 63.57% # Class of executed instruction
|
||||
system.cpu1.op_class::IntAlu 3533248 59.52% 63.56% # Class of executed instruction
|
||||
system.cpu1.op_class::IntMult 9651 0.16% 63.73% # Class of executed instruction
|
||||
system.cpu1.op_class::IntDiv 0 0.00% 63.73% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 7265 0.12% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatAdd 7388 0.12% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCmp 0 0.00% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatCvt 0 0.00% 63.85% # Class of executed instruction
|
||||
system.cpu1.op_class::FloatMult 0 0.00% 63.85% # Class of executed instruction
|
||||
@@ -681,9 +680,9 @@ system.cpu1.op_class::MemRead 1191429 20.07% 83.95% # Cl
|
||||
system.cpu1.op_class::MemWrite 755540 12.73% 96.68% # Class of executed instruction
|
||||
system.cpu1.op_class::IprAccess 197280 3.32% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu1.op_class::total 5935766 # Class of executed instruction
|
||||
system.cpu1.op_class::total 5935771 # Class of executed instruction
|
||||
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2204 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.quiesce 2205 # number of quiesce instructions executed
|
||||
system.cpu1.kern.inst.hwrei 39554 # number of hwrei instructions executed
|
||||
system.cpu1.kern.ipl_count::0 10328 33.46% 33.46% # number of times we switched to this ipl
|
||||
system.cpu1.kern.ipl_count::22 1907 6.18% 39.64% # number of times we switched to this ipl
|
||||
@@ -695,11 +694,11 @@ system.cpu1.kern.ipl_good::22 1907 8.46% 54.23% # nu
|
||||
system.cpu1.kern.ipl_good::30 110 0.49% 54.72% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::31 10208 45.28% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_good::total 22543 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu1.kern.ipl_ticks::0 1859123008500 99.41% 99.41% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::0 1859122617500 99.41% 99.41% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::22 82001000 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::30 14064500 0.00% 99.42% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::31 10905353000 0.58% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::total 1870124427000 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_ticks::total 1870124036000 # number of cycles we spent at this ipl
|
||||
system.cpu1.kern.ipl_used::0 0.999032 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
||||
@@ -751,48 +750,48 @@ system.cpu1.kern.mode_switch_good::kernel 0.592449 # f
|
||||
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::idle 0.015640 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_switch_good::total 0.334518 # fraction of useful protection mode switches
|
||||
system.cpu1.kern.mode_ticks::kernel 1373917500 0.07% 0.07% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::kernel 1373909000 0.07% 0.07% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::user 508289000 0.03% 0.10% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1868002549000 99.90% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.mode_ticks::idle 1868002186500 99.90% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu1.kern.swap_context 471 # number of times the context was actually changed
|
||||
system.cpu1.icache.tags.replacements 103091 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 427.126317 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 5832136 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 103603 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 56.293119 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 1868933059000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126317 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.replacements 103097 # number of replacements
|
||||
system.cpu1.icache.tags.tagsinuse 427.126315 # Cycle average of tags in use
|
||||
system.cpu1.icache.tags.total_refs 5832135 # Total number of references to valid blocks.
|
||||
system.cpu1.icache.tags.sampled_refs 103609 # Sample count of references to valid blocks.
|
||||
system.cpu1.icache.tags.avg_refs 56.289849 # Average number of references to valid blocks.
|
||||
system.cpu1.icache.tags.warmup_cycle 1868932699000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.icache.tags.occ_blocks::cpu1.inst 427.126315 # Average occupied blocks per requestor
|
||||
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.834231 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_percent::total 0.834231 # Average percentage of cache occupancy
|
||||
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id
|
||||
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu1.icache.tags.tag_accesses 6039396 # Number of tag accesses
|
||||
system.cpu1.icache.tags.data_accesses 6039396 # Number of data accesses
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 5832136 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 5832136 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 5832136 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits::total 5832136 # number of demand (read+write) hits
|
||||
system.cpu1.icache.overall_hits::cpu1.inst 5832136 # number of overall hits
|
||||
system.cpu1.icache.overall_hits::total 5832136 # number of overall hits
|
||||
system.cpu1.icache.ReadReq_misses::cpu1.inst 103630 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_misses::total 103630 # number of ReadReq misses
|
||||
system.cpu1.icache.demand_misses::cpu1.inst 103630 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_misses::total 103630 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 103630 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 103630 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 5935766 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 5935766 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses::total 5935766 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::cpu1.inst 5935766 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::total 5935766 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017459 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::total 0.017459 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017459 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_miss_rate::total 0.017459 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017459 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.017459 # miss rate for overall accesses
|
||||
system.cpu1.icache.tags.tag_accesses 6039407 # Number of tag accesses
|
||||
system.cpu1.icache.tags.data_accesses 6039407 # Number of data accesses
|
||||
system.cpu1.icache.ReadReq_hits::cpu1.inst 5832135 # number of ReadReq hits
|
||||
system.cpu1.icache.ReadReq_hits::total 5832135 # number of ReadReq hits
|
||||
system.cpu1.icache.demand_hits::cpu1.inst 5832135 # number of demand (read+write) hits
|
||||
system.cpu1.icache.demand_hits::total 5832135 # number of demand (read+write) hits
|
||||
system.cpu1.icache.overall_hits::cpu1.inst 5832135 # number of overall hits
|
||||
system.cpu1.icache.overall_hits::total 5832135 # number of overall hits
|
||||
system.cpu1.icache.ReadReq_misses::cpu1.inst 103636 # number of ReadReq misses
|
||||
system.cpu1.icache.ReadReq_misses::total 103636 # number of ReadReq misses
|
||||
system.cpu1.icache.demand_misses::cpu1.inst 103636 # number of demand (read+write) misses
|
||||
system.cpu1.icache.demand_misses::total 103636 # number of demand (read+write) misses
|
||||
system.cpu1.icache.overall_misses::cpu1.inst 103636 # number of overall misses
|
||||
system.cpu1.icache.overall_misses::total 103636 # number of overall misses
|
||||
system.cpu1.icache.ReadReq_accesses::cpu1.inst 5935771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.ReadReq_accesses::total 5935771 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.icache.demand_accesses::cpu1.inst 5935771 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.demand_accesses::total 5935771 # number of demand (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::cpu1.inst 5935771 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.overall_accesses::total 5935771 # number of overall (read+write) accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.017460 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.ReadReq_miss_rate::total 0.017460 # miss rate for ReadReq accesses
|
||||
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.017460 # miss rate for demand accesses
|
||||
system.cpu1.icache.demand_miss_rate::total 0.017460 # miss rate for demand accesses
|
||||
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.017460 # miss rate for overall accesses
|
||||
system.cpu1.icache.overall_miss_rate::total 0.017460 # miss rate for overall accesses
|
||||
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -802,45 +801,45 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu1.dcache.tags.replacements 62044 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 421.562730 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 1836054 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 62382 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 29.432432 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 1851115552500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.562730 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823365 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.823365 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.replacements 62047 # number of replacements
|
||||
system.cpu1.dcache.tags.tagsinuse 421.558473 # Cycle average of tags in use
|
||||
system.cpu1.dcache.tags.total_refs 1836050 # Total number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.sampled_refs 62385 # Sample count of references to valid blocks.
|
||||
system.cpu1.dcache.tags.avg_refs 29.430953 # Average number of references to valid blocks.
|
||||
system.cpu1.dcache.tags.warmup_cycle 1851115162500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.558473 # Average occupied blocks per requestor
|
||||
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823356 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_percent::total 0.823356 # Average percentage of cache occupancy
|
||||
system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
|
||||
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
|
||||
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id
|
||||
system.cpu1.dcache.tags.tag_accesses 7735310 # Number of tag accesses
|
||||
system.cpu1.dcache.tags.data_accesses 7735310 # Number of data accesses
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 1109521 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 1109521 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 707457 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 707457 # number of WriteReq hits
|
||||
system.cpu1.dcache.tags.tag_accesses 7735314 # Number of tag accesses
|
||||
system.cpu1.dcache.tags.data_accesses 7735314 # Number of data accesses
|
||||
system.cpu1.dcache.ReadReq_hits::cpu1.data 1109520 # number of ReadReq hits
|
||||
system.cpu1.dcache.ReadReq_hits::total 1109520 # number of ReadReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::cpu1.data 707454 # number of WriteReq hits
|
||||
system.cpu1.dcache.WriteReq_hits::total 707454 # number of WriteReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15133 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.LoadLockedReq_hits::total 15133 # number of LoadLockedReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15610 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.StoreCondReq_hits::total 15610 # number of StoreCondReq hits
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 1816978 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 1816978 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 1816978 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 1816978 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 41444 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 41444 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 25848 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 25848 # number of WriteReq misses
|
||||
system.cpu1.dcache.demand_hits::cpu1.data 1816974 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.demand_hits::total 1816974 # number of demand (read+write) hits
|
||||
system.cpu1.dcache.overall_hits::cpu1.data 1816974 # number of overall hits
|
||||
system.cpu1.dcache.overall_hits::total 1816974 # number of overall hits
|
||||
system.cpu1.dcache.ReadReq_misses::cpu1.data 41445 # number of ReadReq misses
|
||||
system.cpu1.dcache.ReadReq_misses::total 41445 # number of ReadReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::cpu1.data 25851 # number of WriteReq misses
|
||||
system.cpu1.dcache.WriteReq_misses::total 25851 # number of WriteReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1285 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.LoadLockedReq_misses::total 1285 # number of LoadLockedReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 735 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.StoreCondReq_misses::total 735 # number of StoreCondReq misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 67292 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 67292 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 67292 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 67292 # number of overall misses
|
||||
system.cpu1.dcache.demand_misses::cpu1.data 67296 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.demand_misses::total 67296 # number of demand (read+write) misses
|
||||
system.cpu1.dcache.overall_misses::cpu1.data 67296 # number of overall misses
|
||||
system.cpu1.dcache.overall_misses::total 67296 # number of overall misses
|
||||
system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
|
||||
@@ -853,18 +852,18 @@ system.cpu1.dcache.demand_accesses::cpu1.data 1884270
|
||||
system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036008 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.036008 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035249 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.035249 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036009 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.ReadReq_miss_rate::total 0.036009 # miss rate for ReadReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035253 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.WriteReq_miss_rate::total 0.035253 # miss rate for WriteReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078268 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.078268 # miss rate for LoadLockedReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044968 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.044968 # miss rate for StoreCondReq accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035713 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.035713 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035713 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.035713 # miss rate for overall accesses
|
||||
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035715 # miss rate for demand accesses
|
||||
system.cpu1.dcache.demand_miss_rate::total 0.035715 # miss rate for demand accesses
|
||||
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035715 # miss rate for overall accesses
|
||||
system.cpu1.dcache.overall_miss_rate::total 0.035715 # miss rate for overall accesses
|
||||
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -873,8 +872,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu1.dcache.writebacks::writebacks 41012 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 41012 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::writebacks 41020 # number of writebacks
|
||||
system.cpu1.dcache.writebacks::total 41020 # number of writebacks
|
||||
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,55 +1,58 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 1.829332 # Number of seconds simulated
|
||||
sim_ticks 1829332258000 # Number of ticks simulated
|
||||
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 1829332049000 # Number of ticks simulated
|
||||
final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 2367650 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2367648 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 72140813877 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 343680 # Number of bytes of host memory used
|
||||
host_seconds 25.36 # Real time elapsed on the host
|
||||
sim_insts 60038305 # Number of instructions simulated
|
||||
sim_ops 60038305 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 2314619 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 70524837278 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 315304 # Number of bytes of host memory used
|
||||
host_seconds 25.94 # Real time elapsed on the host
|
||||
sim_insts 60038433 # Number of instructions simulated
|
||||
sim_ops 60038433 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 42552540 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 77842734 # Total data (bytes)
|
||||
system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 41099809 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 75185198 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.tags.replacements 41686 # number of replacements
|
||||
system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
@@ -57,26 +60,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 375534 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 375534 # Number of data accesses
|
||||
system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
|
||||
system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits
|
||||
system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
|
||||
system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
|
||||
system.iocache.overall_misses::total 41726 # number of overall misses
|
||||
system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 174 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::tsunami.ide 174 # number of overall misses
|
||||
system.iocache.overall_misses::total 174 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
|
||||
system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
||||
@@ -87,10 +88,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.fast_writes 41552 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 41512 # number of writebacks
|
||||
system.iocache.writebacks::total 41512 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
||||
@@ -109,7 +108,7 @@ system.cpu.dtb.fetch_hits 0 # IT
|
||||
system.cpu.dtb.fetch_misses 0 # ITB misses
|
||||
system.cpu.dtb.fetch_acv 0 # ITB acv
|
||||
system.cpu.dtb.fetch_accesses 0 # ITB accesses
|
||||
system.cpu.dtb.read_hits 9710427 # DTB read hits
|
||||
system.cpu.dtb.read_hits 9710428 # DTB read hits
|
||||
system.cpu.dtb.read_misses 10329 # DTB read misses
|
||||
system.cpu.dtb.read_acv 210 # DTB read access violations
|
||||
system.cpu.dtb.read_accesses 728856 # DTB read accesses
|
||||
@@ -117,14 +116,14 @@ system.cpu.dtb.write_hits 6352498 # DT
|
||||
system.cpu.dtb.write_misses 1142 # DTB write misses
|
||||
system.cpu.dtb.write_acv 157 # DTB write access violations
|
||||
system.cpu.dtb.write_accesses 291931 # DTB write accesses
|
||||
system.cpu.dtb.data_hits 16062925 # DTB hits
|
||||
system.cpu.dtb.data_hits 16062926 # DTB hits
|
||||
system.cpu.dtb.data_misses 11471 # DTB misses
|
||||
system.cpu.dtb.data_acv 367 # DTB access violations
|
||||
system.cpu.dtb.data_accesses 1020787 # DTB accesses
|
||||
system.cpu.itb.fetch_hits 4974648 # ITB hits
|
||||
system.cpu.itb.fetch_hits 4974637 # ITB hits
|
||||
system.cpu.itb.fetch_misses 5006 # ITB misses
|
||||
system.cpu.itb.fetch_acv 184 # ITB acv
|
||||
system.cpu.itb.fetch_accesses 4979654 # ITB accesses
|
||||
system.cpu.itb.fetch_accesses 4979643 # ITB accesses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
system.cpu.itb.read_acv 0 # DTB read access violations
|
||||
@@ -137,34 +136,34 @@ system.cpu.itb.data_hits 0 # DT
|
||||
system.cpu.itb.data_misses 0 # DTB misses
|
||||
system.cpu.itb.data_acv 0 # DTB access violations
|
||||
system.cpu.itb.data_accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 3658664517 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 3658664099 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60038305 # Number of instructions committed
|
||||
system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 60038433 # Number of instructions committed
|
||||
system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 1484182 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913521 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 55913650 # number of integer instructions
|
||||
system.cpu.num_fp_insts 324460 # number of float instructions
|
||||
system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 16115709 # number of memory refs
|
||||
system.cpu.num_load_insts 9747513 # Number of load instructions
|
||||
system.cpu.num_mem_refs 16115710 # number of memory refs
|
||||
system.cpu.num_load_insts 9747514 # Number of load instructions
|
||||
system.cpu.num_store_insts 6368196 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles
|
||||
system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
|
||||
system.cpu.Branches 9064385 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199104 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39460699 65.71% 71.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60680 0.10% 71.14% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.14% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 25609 0.04% 71.18% # Class of executed instruction
|
||||
system.cpu.Branches 9064413 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
|
||||
@@ -190,34 +189,34 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Cl
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975081 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 60050143 # Class of executed instruction
|
||||
system.cpu.op_class::total 60050271 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
|
||||
system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
|
||||
system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
|
||||
system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
|
||||
system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl
|
||||
system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
|
||||
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
|
||||
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
|
||||
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
|
||||
@@ -256,7 +255,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu
|
||||
system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
|
||||
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
|
||||
system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
|
||||
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
|
||||
@@ -265,20 +264,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.93% # nu
|
||||
system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
|
||||
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
|
||||
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192180 # number of callpals executed
|
||||
system.cpu.kern.callpal::total 192179 # number of callpals executed
|
||||
system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
|
||||
system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
|
||||
system.cpu.kern.mode_good::kernel 1909
|
||||
system.cpu.kern.mode_good::user 1738
|
||||
system.cpu.kern.mode_good::kernel 1908
|
||||
system.cpu.kern.mode_good::user 1737
|
||||
system.cpu.kern.mode_good::idle 171
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
|
||||
system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
|
||||
system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode
|
||||
system.cpu.kern.swap_context 4178 # number of times the context was actually changed
|
||||
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
||||
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
||||
@@ -313,13 +312,13 @@ system.tsunami.ethernet.postedInterrupts 0 # nu
|
||||
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
||||
system.iobus.throughput 1480181 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 2707742 # Total data (bytes)
|
||||
system.cpu.icache.tags.replacements 919594 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.replacements 919591 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
@@ -327,26 +326,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 63
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 60970364 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970364 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59129922 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920221 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 59130053 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 920218 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
|
||||
@@ -362,15 +361,15 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 992301 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.replacements 992295 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
|
||||
@@ -379,67 +378,67 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 31737437 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 31737437 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses
|
||||
system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses
|
||||
system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -448,14 +447,14 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74291 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 74285 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 2042702 # number of replacements
|
||||
system.cpu.dcache.tags.replacements 2042683 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
|
||||
@@ -465,52 +464,52 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 443
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 66369799 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369799 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13655992 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026069 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 13656011 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 2026051 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -519,11 +518,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833491 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 833475 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes)
|
||||
system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes)
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,18 +1,56 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 2.332812 # Number of seconds simulated
|
||||
sim_ticks 2332811899500 # Number of ticks simulated
|
||||
final_tick 2332811899500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 2.321351 # Number of seconds simulated
|
||||
sim_ticks 2321351025500 # Number of ticks simulated
|
||||
final_tick 2321351025500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 975328 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 1254205 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 37662621026 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 462792 # Number of bytes of host memory used
|
||||
host_seconds 61.94 # Real time elapsed on the host
|
||||
sim_insts 60411489 # Number of instructions simulated
|
||||
sim_ops 77685090 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 818788 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 985991 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 31464875718 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 430844 # Number of bytes of host memory used
|
||||
host_seconds 73.78 # Real time elapsed on the host
|
||||
sim_insts 60406834 # Number of instructions simulated
|
||||
sim_ops 72742429 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::realview.clcd 110100480 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 705416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9071832 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 119878240 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 705416 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 705416 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3703872 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6719688 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 13762560 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 17234 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141773 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 13921575 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 57873 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 811827 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47429483 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 138 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 83 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 303882 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3907997 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 51641582 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 303882 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 303882 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1595567 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1299164 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2894732 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1595567 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47429483 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 138 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 83 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 303882 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5207161 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54536314 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
||||
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
||||
@@ -25,46 +63,8 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9
|
||||
system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 705160 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 9071768 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 121450784 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 705160 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 705160 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 3703424 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 6719240 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 17230 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 141782 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 14118188 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 57866 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 811820 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::realview.clcd 47870702 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 302279 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 3888770 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 52061970 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 302279 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 302279 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1587536 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1292781 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 2880318 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1587536 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::realview.clcd 47870702 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 302279 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 5181551 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 54942288 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 55969769 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 130566943 # Total data (bytes)
|
||||
system.membus.throughput 55568847 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 128994799 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
||||
@@ -72,8 +72,8 @@ system.cf0.dma_read_txs 0 # Nu
|
||||
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
|
||||
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
|
||||
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
|
||||
system.iobus.throughput 48895283 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 114063499 # Total data (bytes)
|
||||
system.iobus.throughput 48459111 # Throughput (bytes/s)
|
||||
system.iobus.data_through_bus 112490607 # Total data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
@@ -98,25 +98,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT
|
||||
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.dtb.read_hits 14971763 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7294 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11217184 # DTB write hits
|
||||
system.cpu.dtb.read_hits 13142244 # DTB read hits
|
||||
system.cpu.dtb.read_misses 7297 # DTB read misses
|
||||
system.cpu.dtb.write_hits 11216207 # DTB write hits
|
||||
system.cpu.dtb.write_misses 2181 # DTB write misses
|
||||
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
|
||||
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
||||
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
|
||||
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
|
||||
system.cpu.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.flush_entries 3399 # Number of entries that have been flushed from TLB
|
||||
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
||||
system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch
|
||||
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
||||
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.dtb.read_accesses 14979057 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11219365 # DTB write accesses
|
||||
system.cpu.dtb.read_accesses 13149541 # DTB read accesses
|
||||
system.cpu.dtb.write_accesses 11218388 # DTB write accesses
|
||||
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
||||
system.cpu.dtb.hits 26188947 # DTB hits
|
||||
system.cpu.dtb.misses 9475 # DTB misses
|
||||
system.cpu.dtb.accesses 26198422 # DTB accesses
|
||||
system.cpu.dtb.hits 24358451 # DTB hits
|
||||
system.cpu.dtb.misses 9478 # DTB misses
|
||||
system.cpu.dtb.accesses 24367929 # DTB accesses
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
||||
@@ -138,7 +138,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
|
||||
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
||||
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
||||
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
||||
system.cpu.itb.inst_hits 61434680 # ITB inst hits
|
||||
system.cpu.itb.inst_hits 61430007 # ITB inst hits
|
||||
system.cpu.itb.inst_misses 4471 # ITB inst misses
|
||||
system.cpu.itb.read_hits 0 # DTB read hits
|
||||
system.cpu.itb.read_misses 0 # DTB read misses
|
||||
@@ -155,105 +155,107 @@ system.cpu.itb.domain_faults 0 # Nu
|
||||
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
||||
system.cpu.itb.read_accesses 0 # DTB read accesses
|
||||
system.cpu.itb.write_accesses 0 # DTB write accesses
|
||||
system.cpu.itb.inst_accesses 61439151 # ITB inst accesses
|
||||
system.cpu.itb.hits 61434680 # DTB hits
|
||||
system.cpu.itb.inst_accesses 61434478 # ITB inst accesses
|
||||
system.cpu.itb.hits 61430007 # DTB hits
|
||||
system.cpu.itb.misses 4471 # DTB misses
|
||||
system.cpu.itb.accesses 61439151 # DTB accesses
|
||||
system.cpu.numCycles 4665623800 # number of cpu cycles simulated
|
||||
system.cpu.itb.accesses 61434478 # DTB accesses
|
||||
system.cpu.numCycles 4642702052 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 60411489 # Number of instructions committed
|
||||
system.cpu.committedOps 77685090 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 69133554 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 60406834 # Number of instructions committed
|
||||
system.cpu.committedOps 72742429 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 64191430 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2136078 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7942566 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 69133554 # number of integer instructions
|
||||
system.cpu.num_func_calls 2135762 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 7544984 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 64191430 # number of integer instructions
|
||||
system.cpu.num_fp_insts 10269 # number of float instructions
|
||||
system.cpu.num_int_register_reads 355910547 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 74442273 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 116427347 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 42818107 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 27362421 # number of memory refs
|
||||
system.cpu.num_load_insts 15640088 # Number of load instructions
|
||||
system.cpu.num_store_insts 11722333 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4586822073.007144 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 78801726.992856 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.016890 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.983110 # Percentage of idle cycles
|
||||
system.cpu.Branches 10299261 # Number of branches fetched
|
||||
system.cpu.num_cc_register_reads 217570004 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 28977741 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 25221274 # number of memory refs
|
||||
system.cpu.num_load_insts 13499937 # Number of load instructions
|
||||
system.cpu.num_store_insts 11721337 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 4568843017.980124 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 73859034.019877 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.015909 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.984091 # Percentage of idle cycles
|
||||
system.cpu.Branches 10298517 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 28518 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 50337551 64.69% 64.72% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 87780 0.11% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 2117 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.84% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 15640088 20.10% 84.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 11722333 15.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 47536032 65.23% 65.27% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 87771 0.12% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 2113 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.39% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 13499937 18.52% 83.92% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 11721337 16.08% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 77818387 # Class of executed instruction
|
||||
system.cpu.op_class::total 72875708 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 850590 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.678462 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 60586338 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 851102 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 71.185754 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 5711018500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.678462 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999372 # Average percentage of cache occupancy
|
||||
system.cpu.kern.inst.quiesce 82781 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 850515 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 511.689593 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 60581740 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 851027 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 71.186625 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 5455017500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 511.689593 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.999394 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.999394 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 78 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 255 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 62288542 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 62288542 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 60586338 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 60586338 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 60586338 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 60586338 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 60586338 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 60586338 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 851102 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 61437440 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 61437440 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 61437440 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 61437440 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 61437440 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 61437440 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 62283794 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 62283794 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 60581740 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 60581740 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 60581740 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 60581740 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 60581740 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 60581740 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 851027 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 851027 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 851027 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 851027 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 851027 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 851027 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 61432767 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 61432767 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 61432767 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 61432767 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 61432767 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 61432767 # number of overall (read+write) accesses
|
||||
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|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.013853 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.013853 # miss rate for demand accesses
|
||||
@@ -269,115 +271,115 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 62245 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 50007.460447 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1669929 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 127630 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 13.084142 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 2316903124500 # Cycle when the warmup percentage was hit.
|
||||
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|
||||
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|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.716487 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 6089.011961 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.563046 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.replacements 62250 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 50006.834636 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 1669916 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 127635 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 13.083527 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 2306278064000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 36897.866975 # Average occupied blocks per requestor
|
||||
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|
||||
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|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 7014.476656 # Average occupied blocks per requestor
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.092934 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.763044 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3589 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52388 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3672 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9281 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52125 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 17035991 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 17035991 # Number of data accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_hits::total 1216282 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 592648 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 592648 # number of Writeback hits
|
||||
system.cpu.l2cache.tags.tag_accesses 17035648 # Number of tag accesses
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.Writeback_hits::writebacks 592642 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 592642 # number of Writeback hits
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses
|
||||
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|
||||
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|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses
|
||||
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|
||||
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|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539908 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229767 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.103744 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229767 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.103744 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 10608 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 143345 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 153961 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7546 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 849401 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 376661 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 1236762 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 592642 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 592642 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2943 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 2943 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 247180 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7546 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 849401 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 623841 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 1483942 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7546 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 849401 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 623841 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 1483942 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012489 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026207 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.016565 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991165 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991165 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.539987 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.539987 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012489 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229778 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.103751 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012489 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229778 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.103751 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -386,69 +388,77 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 57866 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57866 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 57873 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 57873 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 623343 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997030 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 23629012 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 623855 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 37.875808 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.replacements 623329 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 21798545 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 623841 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 34.942469 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997018 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 278 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 97635323 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 97635323 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 13180574 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 13180574 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9962233 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9962233 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 23142807 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 23142807 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 23142807 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 23142807 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 365463 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 365463 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250154 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250154 # number of WriteReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 615617 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 615617 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 615617 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 615617 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13546037 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13546037 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10212387 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10212387 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 23758424 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 23758424 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 23758424 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 23758424 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026979 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.026979 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
|
||||
system.cpu.dcache.tags.tag_accesses 90313385 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 90313385 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 11240226 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 11240226 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 9961316 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 9961316 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 110856 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 110856 # number of SoftPFReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236008 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 236008 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 247196 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 247196 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 21201542 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 21201542 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 21312398 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 21312398 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 292030 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 292030 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 250123 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 250123 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 73442 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 73442 # number of SoftPFReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11189 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.LoadLockedReq_misses::total 11189 # number of LoadLockedReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 542153 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 542153 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 615595 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 615595 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 11532256 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 11532256 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 10211439 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 10211439 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 184298 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 184298 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247197 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 247197 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247196 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 247196 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21743695 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21743695 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21927993 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21927993 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025323 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.025323 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024494 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.024494 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.398496 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.398496 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045263 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045263 # miss rate for LoadLockedReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.024934 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.024934 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.028073 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.028073 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -457,11 +467,11 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 592648 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 592648 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 592642 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 592642 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 59102995 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 137876171 # Total data (bytes)
|
||||
system.cpu.toL2Bus.throughput 59392167 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 137870067 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.tags.replacements 0 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,63 +1,66 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 5.112126 # Number of seconds simulated
|
||||
sim_ticks 5112126264500 # Number of ticks simulated
|
||||
final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 5112125984500 # Number of ticks simulated
|
||||
final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 1285356 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2631685 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32866027497 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 626676 # Number of bytes of host memory used
|
||||
host_seconds 155.54 # Real time elapsed on the host
|
||||
sim_insts 199929810 # Number of instructions simulated
|
||||
sim_ops 409343850 # Number of ops (including micro ops) simulated
|
||||
host_inst_rate 1274105 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 32578287771 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 593532 # Number of bytes of host memory used
|
||||
host_seconds 156.92 # Real time elapsed on the host
|
||||
sim_insts 199930130 # Number of instructions simulated
|
||||
sim_ops 409344539 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory
|
||||
system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory
|
||||
system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory
|
||||
system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory
|
||||
system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9634332 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 49251923 # Total data (bytes)
|
||||
system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9050072 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 46265107 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.iocache.tags.replacements 47569 # number of replacements
|
||||
system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
|
||||
system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use
|
||||
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
||||
system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
|
||||
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
||||
system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor
|
||||
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
|
||||
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
||||
@@ -65,26 +68,24 @@ system.iocache.tags.age_task_id_blocks_1023::2 16
|
||||
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
||||
system.iocache.tags.tag_accesses 428616 # Number of tag accesses
|
||||
system.iocache.tags.data_accesses 428616 # Number of data accesses
|
||||
system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
|
||||
system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
|
||||
system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
|
||||
system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
|
||||
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
||||
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
|
||||
system.iocache.overall_misses::total 47624 # number of overall misses
|
||||
system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
|
||||
system.iocache.demand_misses::total 904 # number of demand (read+write) misses
|
||||
system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
|
||||
system.iocache.overall_misses::total 904 # number of overall misses
|
||||
system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
|
||||
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
|
||||
system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
|
||||
system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
|
||||
system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
|
||||
system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
|
||||
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
||||
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
||||
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
||||
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
||||
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
||||
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
||||
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
||||
@@ -95,10 +96,8 @@ system.iocache.blocked::no_mshrs 0 # nu
|
||||
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
||||
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.iocache.fast_writes 0 # number of fast writes performed
|
||||
system.iocache.fast_writes 46720 # number of fast writes performed
|
||||
system.iocache.cache_copies 0 # number of cache copies performed
|
||||
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
||||
system.iocache.writebacks::total 46667 # number of writebacks
|
||||
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
||||
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
||||
@@ -116,34 +115,34 @@ system.iobus.throughput 2555207 # Th
|
||||
system.iobus.data_through_bus 13062542 # Total data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
|
||||
system.cpu.numCycles 10224253904 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 10224253344 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 199929810 # Number of instructions committed
|
||||
system.cpu.committedOps 409343850 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses
|
||||
system.cpu.committedInsts 199930130 # Number of instructions committed
|
||||
system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 2307717 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374364636 # number of integer instructions
|
||||
system.cpu.num_func_calls 2307745 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 374365317 # number of integer instructions
|
||||
system.cpu.num_fp_insts 0 # number of float instructions
|
||||
system.cpu.num_int_register_reads 682285475 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323369236 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35660913 # number of memory refs
|
||||
system.cpu.num_load_insts 27238816 # Number of load instructions
|
||||
system.cpu.num_store_insts 8422097 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles
|
||||
system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 35661072 # number of memory refs
|
||||
system.cpu.num_load_insts 27238907 # Number of load instructions
|
||||
system.cpu.num_store_insts 8422165 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
|
||||
system.cpu.Branches 43125514 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 175310 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373241321 91.18% 91.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144368 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.Branches 43125613 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
|
||||
@@ -171,18 +170,18 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Cl
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27238816 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8422097 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 409344880 # Class of executed instruction
|
||||
system.cpu.op_class::total 409345569 # Class of executed instruction
|
||||
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
||||
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
||||
system.cpu.icache.tags.replacements 790558 # number of replacements
|
||||
system.cpu.icache.tags.replacements 790679 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
|
||||
@@ -192,26 +191,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::0 87
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.icache.tags.tag_accesses 245107932 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245107932 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243525778 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791077 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses
|
||||
system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses
|
||||
system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses
|
||||
system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits
|
||||
system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits
|
||||
system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits
|
||||
system.cpu.icache.overall_hits::total 243526070 # number of overall hits
|
||||
system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses
|
||||
system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 791198 # number of overall misses
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
|
||||
@@ -228,12 +227,12 @@ system.cpu.icache.fast_writes 0 # nu
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use
|
||||
system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
|
||||
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
|
||||
@@ -283,12 +282,12 @@ system.cpu.itb_walker_cache.writebacks::writebacks 526
|
||||
system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
|
||||
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use
|
||||
system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks.
|
||||
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
|
||||
@@ -296,32 +295,32 @@ system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
|
||||
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 52398 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 52398 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses
|
||||
system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -333,11 +332,11 @@ system.cpu.dtb_walker_cache.cache_copies 0 # nu
|
||||
system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
|
||||
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 1622097 # number of replacements
|
||||
system.cpu.dcache.tags.replacements 1622084 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
|
||||
@@ -347,40 +346,48 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 226
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 88813841 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88813841 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20172909 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624895 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits
|
||||
system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 20173085 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses
|
||||
system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses
|
||||
system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses
|
||||
system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses
|
||||
system.cpu.dcache.overall_misses::total 1624882 # number of overall misses
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses
|
||||
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -389,23 +396,23 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535825 # number of writebacks
|
||||
system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks
|
||||
system.cpu.dcache.writebacks::total 1535815 # number of writebacks
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.tags.replacements 105999 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks.
|
||||
system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes)
|
||||
system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes)
|
||||
system.cpu.l2cache.tags.replacements 105997 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
||||
@@ -416,32 +423,32 @@ system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20892 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39453 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id
|
||||
system.cpu.l2cache.tags.tag_accesses 32198887 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 32198887 # Number of data accesses
|
||||
system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses
|
||||
system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits
|
||||
system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits
|
||||
system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits
|
||||
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2242331 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.inst 777860 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::cpu.data 1455273 # number of overall hits
|
||||
system.cpu.l2cache.overall_hits::total 2242439 # number of overall hits
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
|
||||
@@ -463,44 +470,44 @@ system.cpu.l2cache.overall_misses::cpu.data 166704 #
|
||||
system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses)
|
||||
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -509,8 +516,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
|
||||
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98156 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks
|
||||
system.cpu.l2cache.writebacks::total 98154 # number of writebacks
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -4,11 +4,11 @@ sim_seconds 0.200409 # Nu
|
||||
sim_ticks 200409284500 # Number of ticks simulated
|
||||
final_tick 4321214250500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 14275836 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 14275831 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5462126987 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 513712 # Number of bytes of host memory used
|
||||
host_seconds 36.69 # Real time elapsed on the host
|
||||
host_inst_rate 23274047 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 23274036 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 8904961694 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 483300 # Number of bytes of host memory used
|
||||
host_seconds 22.51 # Real time elapsed on the host
|
||||
sim_insts 523790075 # Number of instructions simulated
|
||||
sim_ops 523790075 # Number of ops (including micro ops) simulated
|
||||
testsys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
@@ -114,10 +114,10 @@ testsys.cpu.not_idle_fraction 0.050555 # Pe
|
||||
testsys.cpu.idle_fraction 0.949445 # Percentage of idle cycles
|
||||
testsys.cpu.Branches 2929848 # Number of branches fetched
|
||||
testsys.cpu.op_class::No_OpClass 712819 3.52% 3.52% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 12147340 59.95% 63.47% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntAlu 12147338 59.95% 63.47% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntMult 21654 0.11% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::IntDiv 0 0.00% 63.58% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatAdd 4653 0.02% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatAdd 4655 0.02% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatCmp 1 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatCvt 0 0.00% 63.60% # Class of executed instruction
|
||||
testsys.cpu.op_class::FloatMult 0 0.00% 63.60% # Class of executed instruction
|
||||
@@ -372,10 +372,10 @@ drivesys.cpu.not_idle_fraction 0.023766 # Pe
|
||||
drivesys.cpu.idle_fraction 0.976234 # Percentage of idle cycles
|
||||
drivesys.cpu.Branches 2793313 # Number of branches fetched
|
||||
drivesys.cpu.op_class::No_OpClass 623554 3.27% 3.27% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntAlu 11538630 60.57% 63.84% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntAlu 11538627 60.57% 63.84% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntMult 20663 0.11% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::IntDiv 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatAdd 138 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatAdd 141 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatCmp 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatCvt 0 0.00% 63.95% # Class of executed instruction
|
||||
drivesys.cpu.op_class::FloatMult 0 0.00% 63.95% # Class of executed instruction
|
||||
@@ -525,11 +525,11 @@ sim_seconds 0.000407 # Nu
|
||||
sim_ticks 407341500 # Number of ticks simulated
|
||||
final_tick 4321621592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 7312019890 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 7310591323 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 5683411932 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 513712 # Number of bytes of host memory used
|
||||
host_seconds 0.07 # Real time elapsed on the host
|
||||
host_inst_rate 11799945954 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 11797124974 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 9171074905 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 483300 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 523862353 # Number of instructions simulated
|
||||
sim_ops 523862353 # Number of ops (including micro ops) simulated
|
||||
testsys.voltage_domain.voltage 1 # Voltage in Volts
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2870500 # Number of ticks simulated
|
||||
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 2694500 # Number of ticks simulated
|
||||
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 790734 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 984195 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 492029482 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 297624 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 109620 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 128318 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 64270947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 268656 # Number of bytes of host memory used
|
||||
host_seconds 0.04 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
sim_ops 5377 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
|
||||
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 18416 # Nu
|
||||
system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9251001568 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9855260716 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 26555 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
@@ -211,63 +211,65 @@ system.cpu.itb.inst_accesses 0 # IT
|
||||
system.cpu.itb.hits 0 # DTB hits
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.numCycles 5742 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5390 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
|
||||
system.cpu.committedOps 5377 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 203 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4976 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4624 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 25360 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 7607 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2138 # number of memory refs
|
||||
system.cpu.num_load_insts 1200 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 1965 # number of memory refs
|
||||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5742 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5390 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1007 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5742 # Class of executed instruction
|
||||
system.cpu.op_class::total 5390 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2870500 # Number of ticks simulated
|
||||
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 2694500 # Number of ticks simulated
|
||||
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 770690 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 959471 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 479615706 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 296608 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 133655 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 156442 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 78348823 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 267596 # Number of bytes of host memory used
|
||||
host_seconds 0.03 # Real time elapsed on the host
|
||||
sim_insts 4591 # Number of instructions simulated
|
||||
sim_ops 5729 # Number of ops (including micro ops) simulated
|
||||
sim_ops 5377 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
|
||||
@@ -21,21 +21,21 @@ system.physmem.bytes_inst_read::total 18416 # Nu
|
||||
system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
|
||||
system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
|
||||
system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory
|
||||
system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
|
||||
system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9251001568 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 9855260716 # Throughput (bytes/s)
|
||||
system.membus.data_through_bus 26555 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
@@ -124,63 +124,65 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 5742 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 5390 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4591 # Number of instructions committed
|
||||
system.cpu.committedOps 5729 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
|
||||
system.cpu.committedOps 5377 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 203 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4976 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4624 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 25360 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 7607 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2138 # number of memory refs
|
||||
system.cpu.num_load_insts 1200 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 1965 # number of memory refs
|
||||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 5742 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 5390 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1007 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5742 # Class of executed instruction
|
||||
system.cpu.op_class::total 5390 # Class of executed instruction
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,16 +1,16 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000026 # Number of seconds simulated
|
||||
sim_ticks 25969000 # Number of ticks simulated
|
||||
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_ticks 25815000 # Number of ticks simulated
|
||||
final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
host_inst_rate 376681 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 467447 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 2137718143 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306356 # Number of bytes of host memory used
|
||||
host_seconds 0.01 # Real time elapsed on the host
|
||||
host_inst_rate 85918 # Simulator instruction rate (inst/s)
|
||||
host_op_rate 100276 # Simulator op (including micro ops) rate (op/s)
|
||||
host_tick_rate 485659481 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 277384 # Number of bytes of host memory used
|
||||
host_seconds 0.05 # Real time elapsed on the host
|
||||
sim_insts 4565 # Number of instructions simulated
|
||||
sim_ops 5672 # Number of ops (including micro ops) simulated
|
||||
sim_ops 5329 # Number of ops (including micro ops) simulated
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1000 # Clock period in ticks
|
||||
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
|
||||
@@ -21,15 +21,15 @@ system.physmem.bytes_inst_read::total 14400 # Nu
|
||||
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
|
||||
system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
|
||||
system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 862566907 # Throughput (bytes/s)
|
||||
system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s)
|
||||
system.membus.throughput 867712570 # Throughput (bytes/s)
|
||||
system.membus.trans_dist::ReadReq 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadResp 307 # Transaction distribution
|
||||
system.membus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
@@ -40,10 +40,10 @@ system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port
|
||||
system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)
|
||||
system.membus.data_through_bus 22400 # Total data (bytes)
|
||||
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
||||
system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 12.1 # Layer utilization (%)
|
||||
system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks)
|
||||
system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
|
||||
system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks)
|
||||
system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
|
||||
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
||||
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
||||
@@ -130,73 +130,75 @@ system.cpu.itb.hits 0 # DT
|
||||
system.cpu.itb.misses 0 # DTB misses
|
||||
system.cpu.itb.accesses 0 # DTB accesses
|
||||
system.cpu.workload.num_syscalls 13 # Number of system calls
|
||||
system.cpu.numCycles 51938 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 51630 # number of cpu cycles simulated
|
||||
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
||||
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
||||
system.cpu.committedInsts 4565 # Number of instructions committed
|
||||
system.cpu.committedOps 5672 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
|
||||
system.cpu.committedOps 5329 # Number of ops (including micro ops) committed
|
||||
system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
|
||||
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
|
||||
system.cpu.num_func_calls 203 # number of times a function call or return occured
|
||||
system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4976 # number of integer instructions
|
||||
system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
|
||||
system.cpu.num_int_insts 4624 # number of integer instructions
|
||||
system.cpu.num_fp_insts 16 # number of float instructions
|
||||
system.cpu.num_int_register_reads 28821 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
|
||||
system.cpu.num_int_register_reads 7573 # number of times the integer registers were read
|
||||
system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
|
||||
system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
|
||||
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
||||
system.cpu.num_mem_refs 2138 # number of memory refs
|
||||
system.cpu.num_load_insts 1200 # Number of load instructions
|
||||
system.cpu.num_cc_register_reads 19184 # number of times the CC registers were read
|
||||
system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
|
||||
system.cpu.num_mem_refs 1965 # number of memory refs
|
||||
system.cpu.num_load_insts 1027 # Number of load instructions
|
||||
system.cpu.num_store_insts 938 # Number of store instructions
|
||||
system.cpu.num_idle_cycles 0 # Number of idle cycles
|
||||
system.cpu.num_busy_cycles 51938 # Number of busy cycles
|
||||
system.cpu.num_busy_cycles 51630 # Number of busy cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.Branches 1007 # Number of branches fetched
|
||||
system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction
|
||||
system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction
|
||||
system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
|
||||
system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
||||
system.cpu.op_class::total 5742 # Class of executed instruction
|
||||
system.cpu.op_class::total 5390 # Class of executed instruction
|
||||
system.cpu.icache.tags.replacements 1 # number of replacements
|
||||
system.cpu.icache.tags.tagsinuse 114.614391 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use
|
||||
system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks.
|
||||
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.614391 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055964 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor
|
||||
system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy
|
||||
system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
|
||||
system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
|
||||
@@ -215,12 +217,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n
|
||||
system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
|
||||
system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
|
||||
system.cpu.icache.overall_misses::total 241 # number of overall misses
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12583000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12583000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12583000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12583000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12583000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12583000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles
|
||||
system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles
|
||||
system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses
|
||||
@@ -233,12 +235,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334
|
||||
system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses
|
||||
system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52211.618257 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52211.618257 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52211.618257 # average overall miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency
|
||||
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -253,36 +255,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241
|
||||
system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.tags.tagsinuse 154.071129 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.889758 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.181371 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003231 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004702 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy
|
||||
system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
|
||||
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
|
||||
@@ -309,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu
|
||||
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
|
||||
system.cpu.l2cache.overall_misses::total 350 # number of overall misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses)
|
||||
@@ -342,17 +344,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 #
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency
|
||||
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
||||
@@ -407,32 +409,32 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.tags.replacements 0 # number of replacements
|
||||
system.cpu.dcache.tags.tagsinuse 83.000387 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1940 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use
|
||||
system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 13.758865 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020264 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor
|
||||
system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy
|
||||
system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
|
||||
system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
|
||||
system.cpu.dcache.tags.tag_accesses 4303 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 4303 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
|
||||
system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
|
||||
system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
|
||||
system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
|
||||
system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1918 # number of overall hits
|
||||
system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits
|
||||
system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits
|
||||
system.cpu.dcache.overall_hits::total 1764 # number of overall hits
|
||||
system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
|
||||
system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
|
||||
@@ -449,26 +451,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7083000
|
||||
system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
|
||||
system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
|
||||
system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
|
||||
system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
|
||||
@@ -501,14 +503,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000
|
||||
system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
|
||||
@@ -518,7 +520,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.throughput 947046291 # Throughput (bytes/s)
|
||||
system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
|
||||
system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,529 +1,529 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.008665 # Number of seconds simulated
|
||||
sim_ticks 8664886 # Number of ticks simulated
|
||||
final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.008851 # Number of seconds simulated
|
||||
sim_ticks 8851106 # Number of ticks simulated
|
||||
final_tick 8851106 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 160889 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 306216 # Number of bytes of host memory used
|
||||
host_seconds 53.86 # Real time elapsed on the host
|
||||
host_tick_rate 251677 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 263028 # Number of bytes of host memory used
|
||||
host_seconds 35.17 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 4 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 39 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1237687 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.014190 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 0.298328 # delay histogram for all message
|
||||
system.ruby.delayHist | 1235151 99.80% 99.80% | 1617 0.13% 99.93% | 897 0.07% 100.00% | 6 0.00% 100.00% | 12 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1237687 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 1264357 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 0.014702 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 0.302971 # delay histogram for all message
|
||||
system.ruby.delayHist | 1261652 99.79% 99.79% | 1743 0.14% 99.92% | 940 0.07% 100.00% | 5 0.00% 100.00% | 13 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 1264357 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 2
|
||||
system.ruby.outstanding_req_hist::max_bucket 19
|
||||
system.ruby.outstanding_req_hist::samples 617680
|
||||
system.ruby.outstanding_req_hist::mean 15.998443
|
||||
system.ruby.outstanding_req_hist::gmean 15.997160
|
||||
system.ruby.outstanding_req_hist::stdev 0.126732
|
||||
system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 18 0.00% 0.02% | 617558 99.98% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 617680
|
||||
system.ruby.outstanding_req_hist::samples 630979
|
||||
system.ruby.outstanding_req_hist::mean 15.998479
|
||||
system.ruby.outstanding_req_hist::gmean 15.997223
|
||||
system.ruby.outstanding_req_hist::stdev 0.125377
|
||||
system.ruby.outstanding_req_hist | 8 0.00% 0.00% | 16 0.00% 0.00% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.01% | 16 0.00% 0.02% | 16 0.00% 0.02% | 630859 99.98% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 630979
|
||||
system.ruby.latency_hist::bucket_size 512
|
||||
system.ruby.latency_hist::max_bucket 5119
|
||||
system.ruby.latency_hist::samples 617552
|
||||
system.ruby.latency_hist::mean 1795.769022
|
||||
system.ruby.latency_hist::gmean 1749.288930
|
||||
system.ruby.latency_hist::stdev 410.975839
|
||||
system.ruby.latency_hist | 49 0.01% 0.01% | 8521 1.38% 1.39% | 161856 26.21% 27.60% | 292941 47.44% 75.03% | 127050 20.57% 95.61% | 24164 3.91% 99.52% | 2669 0.43% 99.95% | 258 0.04% 99.99% | 42 0.01% 100.00% | 2 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 617552
|
||||
system.ruby.latency_hist::samples 630851
|
||||
system.ruby.latency_hist::mean 1795.719672
|
||||
system.ruby.latency_hist::gmean 1748.933148
|
||||
system.ruby.latency_hist::stdev 412.147444
|
||||
system.ruby.latency_hist | 49 0.01% 0.01% | 8914 1.41% 1.42% | 165687 26.26% 27.68% | 297783 47.20% 74.89% | 130737 20.72% 95.61% | 24608 3.90% 99.51% | 2780 0.44% 99.95% | 265 0.04% 100.00% | 24 0.00% 100.00% | 4 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 630851
|
||||
system.ruby.miss_latency_hist::bucket_size 512
|
||||
system.ruby.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.miss_latency_hist::samples 617552
|
||||
system.ruby.miss_latency_hist::mean 1795.769022
|
||||
system.ruby.miss_latency_hist::gmean 1749.288930
|
||||
system.ruby.miss_latency_hist::stdev 410.975839
|
||||
system.ruby.miss_latency_hist | 49 0.01% 0.01% | 8521 1.38% 1.39% | 161856 26.21% 27.60% | 292941 47.44% 75.03% | 127050 20.57% 95.61% | 24164 3.91% 99.52% | 2669 0.43% 99.95% | 258 0.04% 99.99% | 42 0.01% 100.00% | 2 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 617552
|
||||
system.ruby.L1Cache.incomplete_times 8208
|
||||
system.ruby.Directory.incomplete_times 609337
|
||||
system.ruby.miss_latency_hist::samples 630851
|
||||
system.ruby.miss_latency_hist::mean 1795.719672
|
||||
system.ruby.miss_latency_hist::gmean 1748.933148
|
||||
system.ruby.miss_latency_hist::stdev 412.147444
|
||||
system.ruby.miss_latency_hist | 49 0.01% 0.01% | 8914 1.41% 1.42% | 165687 26.26% 27.68% | 297783 47.20% 74.89% | 130737 20.72% 95.61% | 24608 3.90% 99.51% | 2780 0.44% 99.95% | 265 0.04% 100.00% | 24 0.00% 100.00% | 4 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 630851
|
||||
system.ruby.L1Cache.incomplete_times 8485
|
||||
system.ruby.Directory.incomplete_times 622362
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_misses 77331 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_accesses 77331 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_misses 78801 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl4.cacheMemory.demand_accesses 78801 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_misses 77389 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_accesses 77389 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_misses 78712 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl5.cacheMemory.demand_accesses 78712 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_misses 77354 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_accesses 77354 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_misses 78682 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl6.cacheMemory.demand_accesses 78682 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_misses 77281 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_accesses 77281 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_misses 79132 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl7.cacheMemory.demand_accesses 79132 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 77377 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 77377 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_misses 78906 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 78906 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_misses 77193 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_accesses 77193 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_misses 78862 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl1.cacheMemory.demand_accesses 78862 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_misses 76824 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_accesses 76824 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_misses 78717 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl2.cacheMemory.demand_accesses 78717 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_misses 76825 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_accesses 76825 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 4.474669
|
||||
system.ruby.network.routers0.msg_count.Control::2 77377
|
||||
system.ruby.network.routers0.msg_count.Data::2 76667
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 78423
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 77713
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 619016
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 5520024
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 5646456
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 621704
|
||||
system.ruby.network.routers1.percent_links_utilized 4.463498
|
||||
system.ruby.network.routers1.msg_count.Control::2 77193
|
||||
system.ruby.network.routers1.msg_count.Data::2 76469
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 78234
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 77508
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 617544
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 5505768
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 5632848
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 620064
|
||||
system.ruby.network.routers2.percent_links_utilized 4.442205
|
||||
system.ruby.network.routers2.msg_count.Control::2 76824
|
||||
system.ruby.network.routers2.msg_count.Data::2 76104
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 77861
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 77139
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 614592
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 5479488
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 5605992
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 617112
|
||||
system.ruby.network.routers3.percent_links_utilized 4.442687
|
||||
system.ruby.network.routers3.msg_count.Control::2 76823
|
||||
system.ruby.network.routers3.msg_count.Data::2 76096
|
||||
system.ruby.network.routers3.msg_count.Response_Data::4 77886
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::3 77157
|
||||
system.ruby.network.routers3.msg_bytes.Control::2 614584
|
||||
system.ruby.network.routers3.msg_bytes.Data::2 5478912
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::4 5607792
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::3 617256
|
||||
system.ruby.network.routers4.percent_links_utilized 4.471582
|
||||
system.ruby.network.routers4.msg_count.Control::2 77331
|
||||
system.ruby.network.routers4.msg_count.Data::2 76659
|
||||
system.ruby.network.routers4.msg_count.Response_Data::4 78324
|
||||
system.ruby.network.routers4.msg_count.Writeback_Control::3 77652
|
||||
system.ruby.network.routers4.msg_bytes.Control::2 618648
|
||||
system.ruby.network.routers4.msg_bytes.Data::2 5519448
|
||||
system.ruby.network.routers4.msg_bytes.Response_Data::4 5639328
|
||||
system.ruby.network.routers4.msg_bytes.Writeback_Control::3 621216
|
||||
system.ruby.network.routers5.percent_links_utilized 4.475356
|
||||
system.ruby.network.routers5.msg_count.Control::2 77389
|
||||
system.ruby.network.routers5.msg_count.Data::2 76728
|
||||
system.ruby.network.routers5.msg_count.Response_Data::4 78386
|
||||
system.ruby.network.routers5.msg_count.Writeback_Control::3 77723
|
||||
system.ruby.network.routers5.msg_bytes.Control::2 619112
|
||||
system.ruby.network.routers5.msg_bytes.Data::2 5524416
|
||||
system.ruby.network.routers5.msg_bytes.Response_Data::4 5643792
|
||||
system.ruby.network.routers5.msg_bytes.Writeback_Control::3 621784
|
||||
system.ruby.network.routers6.percent_links_utilized 4.472419
|
||||
system.ruby.network.routers6.msg_count.Control::2 77354
|
||||
system.ruby.network.routers6.msg_count.Data::2 76662
|
||||
system.ruby.network.routers6.msg_count.Response_Data::4 78350
|
||||
system.ruby.network.routers6.msg_count.Writeback_Control::3 77658
|
||||
system.ruby.network.routers6.msg_bytes.Control::2 618832
|
||||
system.ruby.network.routers6.msg_bytes.Data::2 5519664
|
||||
system.ruby.network.routers6.msg_bytes.Response_Data::4 5641200
|
||||
system.ruby.network.routers6.msg_bytes.Writeback_Control::3 621264
|
||||
system.ruby.network.routers7.percent_links_utilized 4.468123
|
||||
system.ruby.network.routers7.msg_count.Control::2 77277
|
||||
system.ruby.network.routers7.msg_count.Data::2 76568
|
||||
system.ruby.network.routers7.msg_count.Response_Data::4 78296
|
||||
system.ruby.network.routers7.msg_count.Writeback_Control::3 77585
|
||||
system.ruby.network.routers7.msg_bytes.Control::2 618216
|
||||
system.ruby.network.routers7.msg_bytes.Data::2 5512896
|
||||
system.ruby.network.routers7.msg_bytes.Response_Data::4 5637312
|
||||
system.ruby.network.routers7.msg_bytes.Writeback_Control::3 620680
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_misses 79057 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl3.cacheMemory.demand_accesses 79057 # Number of cache demand accesses
|
||||
system.ruby.network.routers0.percent_links_utilized 4.466411
|
||||
system.ruby.network.routers0.msg_count.Control::2 78906
|
||||
system.ruby.network.routers0.msg_count.Data::2 78209
|
||||
system.ruby.network.routers0.msg_count.Response_Data::4 79922
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::3 79222
|
||||
system.ruby.network.routers0.msg_bytes.Control::2 631248
|
||||
system.ruby.network.routers0.msg_bytes.Data::2 5631048
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::4 5754384
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 633776
|
||||
system.ruby.network.routers1.percent_links_utilized 4.464072
|
||||
system.ruby.network.routers1.msg_count.Control::2 78862
|
||||
system.ruby.network.routers1.msg_count.Data::2 78116
|
||||
system.ruby.network.routers1.msg_count.Response_Data::4 79932
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::3 79185
|
||||
system.ruby.network.routers1.msg_bytes.Control::2 630896
|
||||
system.ruby.network.routers1.msg_bytes.Data::2 5624352
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::4 5755104
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 633480
|
||||
system.ruby.network.routers2.percent_links_utilized 4.456923
|
||||
system.ruby.network.routers2.msg_count.Control::2 78717
|
||||
system.ruby.network.routers2.msg_count.Data::2 78011
|
||||
system.ruby.network.routers2.msg_count.Response_Data::4 79784
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::3 79076
|
||||
system.ruby.network.routers2.msg_bytes.Control::2 629736
|
||||
system.ruby.network.routers2.msg_bytes.Data::2 5616792
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::4 5744448
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 632608
|
||||
system.ruby.network.routers3.percent_links_utilized 4.475147
|
||||
system.ruby.network.routers3.msg_count.Control::2 79057
|
||||
system.ruby.network.routers3.msg_count.Data::2 78335
|
||||
system.ruby.network.routers3.msg_count.Response_Data::4 80105
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::3 79383
|
||||
system.ruby.network.routers3.msg_bytes.Control::2 632456
|
||||
system.ruby.network.routers3.msg_bytes.Data::2 5640120
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::4 5767560
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::3 635064
|
||||
system.ruby.network.routers4.percent_links_utilized 4.460937
|
||||
system.ruby.network.routers4.msg_count.Control::2 78801
|
||||
system.ruby.network.routers4.msg_count.Data::2 78061
|
||||
system.ruby.network.routers4.msg_count.Response_Data::4 79876
|
||||
system.ruby.network.routers4.msg_count.Writeback_Control::3 79135
|
||||
system.ruby.network.routers4.msg_bytes.Control::2 630408
|
||||
system.ruby.network.routers4.msg_bytes.Data::2 5620392
|
||||
system.ruby.network.routers4.msg_bytes.Response_Data::4 5751072
|
||||
system.ruby.network.routers4.msg_bytes.Writeback_Control::3 633080
|
||||
system.ruby.network.routers5.percent_links_utilized 4.455593
|
||||
system.ruby.network.routers5.msg_count.Control::2 78712
|
||||
system.ruby.network.routers5.msg_count.Data::2 77972
|
||||
system.ruby.network.routers5.msg_count.Response_Data::4 79776
|
||||
system.ruby.network.routers5.msg_count.Writeback_Control::3 79033
|
||||
system.ruby.network.routers5.msg_bytes.Control::2 629696
|
||||
system.ruby.network.routers5.msg_bytes.Data::2 5613984
|
||||
system.ruby.network.routers5.msg_bytes.Response_Data::4 5743872
|
||||
system.ruby.network.routers5.msg_bytes.Writeback_Control::3 632264
|
||||
system.ruby.network.routers6.percent_links_utilized 4.454384
|
||||
system.ruby.network.routers6.msg_count.Control::2 78682
|
||||
system.ruby.network.routers6.msg_count.Data::2 77916
|
||||
system.ruby.network.routers6.msg_count.Response_Data::4 79789
|
||||
system.ruby.network.routers6.msg_count.Writeback_Control::3 79022
|
||||
system.ruby.network.routers6.msg_bytes.Control::2 629456
|
||||
system.ruby.network.routers6.msg_bytes.Data::2 5609952
|
||||
system.ruby.network.routers6.msg_bytes.Response_Data::4 5744808
|
||||
system.ruby.network.routers6.msg_bytes.Writeback_Control::3 632176
|
||||
system.ruby.network.routers7.percent_links_utilized 4.479124
|
||||
system.ruby.network.routers7.msg_count.Control::2 79132
|
||||
system.ruby.network.routers7.msg_count.Data::2 78429
|
||||
system.ruby.network.routers7.msg_count.Response_Data::4 80152
|
||||
system.ruby.network.routers7.msg_count.Writeback_Control::3 79450
|
||||
system.ruby.network.routers7.msg_bytes.Control::2 633056
|
||||
system.ruby.network.routers7.msg_bytes.Data::2 5646888
|
||||
system.ruby.network.routers7.msg_bytes.Response_Data::4 5770944
|
||||
system.ruby.network.routers7.msg_bytes.Writeback_Control::3 635600
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1218678 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 609346 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 609308 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 60173 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 45858057 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 1522193 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 40100008 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 87480258 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 71.782914 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 7076344 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 12585722 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4642017 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1076094 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 9195209 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 11282671 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 38404 3.15% 3.15% | 37646 3.09% 6.24% | 38381 3.15% 9.39% | 38273 3.14% 12.53% | 38109 3.13% 15.66% | 38021 3.12% 18.78% | 38580 3.17% 21.94% | 38357 3.15% 25.09% | 38057 3.12% 28.21% | 38004 3.12% 31.33% | 38123 3.13% 34.46% | 37658 3.09% 37.55% | 37751 3.10% 40.65% | 38546 3.16% 43.81% | 37560 3.08% 46.89% | 38514 3.16% 50.05% | 38232 3.14% 53.19% | 38045 3.12% 56.31% | 38749 3.18% 59.49% | 38589 3.17% 62.66% | 38066 3.12% 65.78% | 37687 3.09% 68.87% | 38032 3.12% 71.99% | 38060 3.12% 75.12% | 37804 3.10% 78.22% | 38206 3.14% 81.35% | 37726 3.10% 84.45% | 38148 3.13% 87.58% | 37682 3.09% 90.67% | 38049 3.12% 93.79% | 37701 3.09% 96.89% | 37918 3.11% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1218678 # Number of accesses per bank
|
||||
system.ruby.network.routers8.percent_links_utilized 35.284146
|
||||
system.ruby.network.routers8.msg_count.Control::2 617562
|
||||
system.ruby.network.routers8.msg_count.Data::2 611948
|
||||
system.ruby.network.routers8.msg_count.Response_Data::4 609345
|
||||
system.ruby.network.routers8.msg_count.Writeback_Control::3 620135
|
||||
system.ruby.network.routers8.msg_bytes.Control::2 4940496
|
||||
system.ruby.network.routers8.msg_bytes.Data::2 44060256
|
||||
system.ruby.network.routers8.msg_bytes.Response_Data::4 43872840
|
||||
system.ruby.network.routers8.msg_bytes.Writeback_Control::3 4961080
|
||||
system.ruby.network.routers9.percent_links_utilized 7.888285
|
||||
system.ruby.network.routers9.msg_count.Control::2 617562
|
||||
system.ruby.network.routers9.msg_count.Data::2 611948
|
||||
system.ruby.network.routers9.msg_count.Response_Data::4 617553
|
||||
system.ruby.network.routers9.msg_count.Writeback_Control::3 620135
|
||||
system.ruby.network.routers9.msg_bytes.Control::2 4940496
|
||||
system.ruby.network.routers9.msg_bytes.Data::2 44060256
|
||||
system.ruby.network.routers9.msg_bytes.Response_Data::4 44463816
|
||||
system.ruby.network.routers9.msg_bytes.Writeback_Control::3 4961080
|
||||
system.ruby.network.msg_count.Control 1852692
|
||||
system.ruby.network.msg_count.Data 1835849
|
||||
system.ruby.network.msg_count.Response_Data 1852658
|
||||
system.ruby.network.msg_count.Writeback_Control 1860405
|
||||
system.ruby.network.msg_byte.Control 14821536
|
||||
system.ruby.network.msg_byte.Data 132181128
|
||||
system.ruby.network.msg_byte.Response_Data 133391376
|
||||
system.ruby.network.msg_byte.Writeback_Control 14883240
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1244736 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 622369 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 622327 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 61466 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 46843919 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 1544719 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 40914855 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 89303493 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 71.744927 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 7226521 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 12850865 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 4733152 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 1096174 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 9395532 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memNotOld 11541675 # memory stalls due to anti starvation
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 39236 3.15% 3.15% | 39187 3.15% 6.30% | 38854 3.12% 9.42% | 39063 3.14% 12.56% | 38454 3.09% 15.65% | 39210 3.15% 18.80% | 39083 3.14% 21.94% | 39085 3.14% 25.08% | 38983 3.13% 28.21% | 39280 3.16% 31.37% | 39090 3.14% 34.51% | 38371 3.08% 37.59% | 38752 3.11% 40.70% | 38808 3.12% 43.82% | 39073 3.14% 46.96% | 38752 3.11% 50.07% | 38633 3.10% 53.18% | 39174 3.15% 56.32% | 38907 3.13% 59.45% | 39057 3.14% 62.59% | 38471 3.09% 65.68% | 38694 3.11% 68.79% | 38561 3.10% 71.88% | 38553 3.10% 74.98% | 38571 3.10% 78.08% | 38875 3.12% 81.20% | 39085 3.14% 84.34% | 39006 3.13% 87.48% | 39194 3.15% 90.63% | 38693 3.11% 93.74% | 38713 3.11% 96.85% | 39268 3.15% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1244736 # Number of accesses per bank
|
||||
system.ruby.network.routers8.percent_links_utilized 35.281218
|
||||
system.ruby.network.routers8.msg_count.Control::2 630869
|
||||
system.ruby.network.routers8.msg_count.Data::2 625049
|
||||
system.ruby.network.routers8.msg_count.Response_Data::4 622367
|
||||
system.ruby.network.routers8.msg_count.Writeback_Control::3 633506
|
||||
system.ruby.network.routers8.msg_bytes.Control::2 5046952
|
||||
system.ruby.network.routers8.msg_bytes.Data::2 45003528
|
||||
system.ruby.network.routers8.msg_bytes.Response_Data::4 44810424
|
||||
system.ruby.network.routers8.msg_bytes.Writeback_Control::3 5068048
|
||||
system.ruby.network.routers9.percent_links_utilized 7.888201
|
||||
system.ruby.network.routers9.msg_count.Control::2 630869
|
||||
system.ruby.network.routers9.msg_count.Data::2 625049
|
||||
system.ruby.network.routers9.msg_count.Response_Data::4 630851
|
||||
system.ruby.network.routers9.msg_count.Writeback_Control::3 633506
|
||||
system.ruby.network.routers9.msg_bytes.Control::2 5046952
|
||||
system.ruby.network.routers9.msg_bytes.Data::2 45003528
|
||||
system.ruby.network.routers9.msg_bytes.Response_Data::4 45421272
|
||||
system.ruby.network.routers9.msg_bytes.Writeback_Control::3 5068048
|
||||
system.ruby.network.msg_count.Control 1892607
|
||||
system.ruby.network.msg_count.Data 1875147
|
||||
system.ruby.network.msg_count.Response_Data 1892554
|
||||
system.ruby.network.msg_count.Writeback_Control 1900518
|
||||
system.ruby.network.msg_byte.Control 15140856
|
||||
system.ruby.network.msg_byte.Data 135010584
|
||||
system.ruby.network.msg_byte.Response_Data 136263888
|
||||
system.ruby.network.msg_byte.Writeback_Control 15204144
|
||||
system.funcbus.throughput 0 # Throughput (bytes/s)
|
||||
system.funcbus.data_through_bus 0 # Total data (bytes)
|
||||
system.cpu_clk_domain.clock 1 # Clock period in ticks
|
||||
system.cpu0.num_reads 99885 # number of read accesses completed
|
||||
system.cpu0.num_writes 54375 # number of write accesses completed
|
||||
system.cpu0.num_reads 99672 # number of read accesses completed
|
||||
system.cpu0.num_writes 55456 # number of write accesses completed
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99537 # number of read accesses completed
|
||||
system.cpu1.num_writes 53839 # number of write accesses completed
|
||||
system.cpu1.num_reads 99787 # number of read accesses completed
|
||||
system.cpu1.num_writes 55562 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99297 # number of read accesses completed
|
||||
system.cpu2.num_writes 53929 # number of write accesses completed
|
||||
system.cpu2.num_reads 99865 # number of read accesses completed
|
||||
system.cpu2.num_writes 55847 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 99124 # number of read accesses completed
|
||||
system.cpu3.num_writes 54072 # number of write accesses completed
|
||||
system.cpu3.num_reads 99798 # number of read accesses completed
|
||||
system.cpu3.num_writes 55621 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99259 # number of read accesses completed
|
||||
system.cpu4.num_writes 54427 # number of write accesses completed
|
||||
system.cpu4.num_reads 99867 # number of read accesses completed
|
||||
system.cpu4.num_writes 55560 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99389 # number of read accesses completed
|
||||
system.cpu5.num_writes 54074 # number of write accesses completed
|
||||
system.cpu5.num_reads 99021 # number of read accesses completed
|
||||
system.cpu5.num_writes 55459 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99658 # number of read accesses completed
|
||||
system.cpu6.num_writes 54033 # number of write accesses completed
|
||||
system.cpu6.num_reads 99570 # number of read accesses completed
|
||||
system.cpu6.num_writes 55395 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53796 # number of write accesses completed
|
||||
system.cpu7.num_writes 56251 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.ruby.network.routers0.throttle0.link_utilization 4.466810
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 77375
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 77713
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5571000
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 621704
|
||||
system.ruby.network.routers0.throttle1.link_utilization 4.482529
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 77377
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 76667
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1048
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 619016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5520024
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 75456
|
||||
system.ruby.network.routers1.throttle0.link_utilization 4.456123
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 77192
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 77508
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5557824
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 620064
|
||||
system.ruby.network.routers1.throttle1.link_utilization 4.470872
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::2 77193
|
||||
system.ruby.network.routers1.throttle1.msg_count.Data::2 76469
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1042
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Control::2 617544
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5505768
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 75024
|
||||
system.ruby.network.routers2.throttle0.link_utilization 4.434727
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 76821
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 77139
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5531112
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 617112
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.449683
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 76824
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 76104
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1040
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 614592
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5479488
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 74880
|
||||
system.ruby.network.routers3.throttle0.link_utilization 4.434830
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 76821
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 77157
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5531112
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 617256
|
||||
system.ruby.network.routers3.throttle1.link_utilization 4.450543
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::2 76823
|
||||
system.ruby.network.routers3.throttle1.msg_count.Data::2 76096
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1065
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Control::2 614584
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5478912
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 76680
|
||||
system.ruby.network.routers4.throttle0.link_utilization 4.464069
|
||||
system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 77329
|
||||
system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 77652
|
||||
system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5567688
|
||||
system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 621216
|
||||
system.ruby.network.routers4.throttle1.link_utilization 4.479095
|
||||
system.ruby.network.routers4.throttle1.msg_count.Control::2 77331
|
||||
system.ruby.network.routers4.throttle1.msg_count.Data::2 76659
|
||||
system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 995
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Control::2 618648
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5519448
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 71640
|
||||
system.ruby.network.routers5.throttle0.link_utilization 4.467387
|
||||
system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 77385
|
||||
system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 77723
|
||||
system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5571720
|
||||
system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 621784
|
||||
system.ruby.network.routers5.throttle1.link_utilization 4.483325
|
||||
system.ruby.network.routers5.throttle1.msg_count.Control::2 77389
|
||||
system.ruby.network.routers5.throttle1.msg_count.Data::2 76728
|
||||
system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1001
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Control::2 619112
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5524416
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 72072
|
||||
system.ruby.network.routers6.throttle0.link_utilization 4.465298
|
||||
system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 77352
|
||||
system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 77658
|
||||
system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5569344
|
||||
system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 621264
|
||||
system.ruby.network.routers6.throttle1.link_utilization 4.479540
|
||||
system.ruby.network.routers6.throttle1.msg_count.Control::2 77354
|
||||
system.ruby.network.routers6.throttle1.msg_count.Data::2 76662
|
||||
system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 998
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Control::2 618832
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5519664
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 71856
|
||||
system.ruby.network.routers7.throttle0.link_utilization 4.460982
|
||||
system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 77277
|
||||
system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 77585
|
||||
system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5563944
|
||||
system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 620680
|
||||
system.ruby.network.routers7.throttle1.link_utilization 4.475264
|
||||
system.ruby.network.routers7.throttle1.msg_count.Control::2 77277
|
||||
system.ruby.network.routers7.throttle1.msg_count.Data::2 76568
|
||||
system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1019
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Control::2 618216
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5512896
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 73368
|
||||
system.ruby.network.routers8.throttle0.link_utilization 35.344302
|
||||
system.ruby.network.routers8.throttle0.msg_count.Control::2 617562
|
||||
system.ruby.network.routers8.throttle0.msg_count.Data::2 611948
|
||||
system.ruby.network.routers8.throttle0.msg_bytes.Control::2 4940496
|
||||
system.ruby.network.routers8.throttle0.msg_bytes.Data::2 44060256
|
||||
system.ruby.network.routers8.throttle1.link_utilization 35.223989
|
||||
system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 609345
|
||||
system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 620135
|
||||
system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 43872840
|
||||
system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 4961080
|
||||
system.ruby.network.routers9.throttle0.link_utilization 4.466810
|
||||
system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 77375
|
||||
system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 77713
|
||||
system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5571000
|
||||
system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 621704
|
||||
system.ruby.network.routers9.throttle1.link_utilization 4.456123
|
||||
system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 77192
|
||||
system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 77508
|
||||
system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5557824
|
||||
system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 620064
|
||||
system.ruby.network.routers9.throttle2.link_utilization 4.434727
|
||||
system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 76821
|
||||
system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 77139
|
||||
system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5531112
|
||||
system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 617112
|
||||
system.ruby.network.routers9.throttle3.link_utilization 4.434830
|
||||
system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 76821
|
||||
system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 77157
|
||||
system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5531112
|
||||
system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 617256
|
||||
system.ruby.network.routers9.throttle4.link_utilization 4.464081
|
||||
system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 77330
|
||||
system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 77652
|
||||
system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5567760
|
||||
system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 621216
|
||||
system.ruby.network.routers9.throttle5.link_utilization 4.467387
|
||||
system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 77385
|
||||
system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 77723
|
||||
system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5571720
|
||||
system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 621784
|
||||
system.ruby.network.routers9.throttle6.link_utilization 4.465298
|
||||
system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 77352
|
||||
system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 77658
|
||||
system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5569344
|
||||
system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 621264
|
||||
system.ruby.network.routers9.throttle7.link_utilization 4.460982
|
||||
system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 77277
|
||||
system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 77585
|
||||
system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5563944
|
||||
system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 620680
|
||||
system.ruby.network.routers9.throttle8.link_utilization 35.344325
|
||||
system.ruby.network.routers9.throttle8.msg_count.Control::2 617562
|
||||
system.ruby.network.routers9.throttle8.msg_count.Data::2 611948
|
||||
system.ruby.network.routers9.throttle8.msg_bytes.Control::2 4940496
|
||||
system.ruby.network.routers9.throttle8.msg_bytes.Data::2 44060256
|
||||
system.ruby.network.routers0.throttle0.link_utilization 4.459092
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 78904
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 79222
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 5681088
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 633776
|
||||
system.ruby.network.routers0.throttle1.link_utilization 4.473729
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::2 78906
|
||||
system.ruby.network.routers0.throttle1.msg_count.Data::2 78209
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Data::4 1018
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 631248
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 5631048
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::4 73296
|
||||
system.ruby.network.routers1.throttle0.link_utilization 4.456697
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::4 78861
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::3 79185
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::4 5677992
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::3 633480
|
||||
system.ruby.network.routers1.throttle1.link_utilization 4.471447
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::2 78862
|
||||
system.ruby.network.routers1.throttle1.msg_count.Data::2 78116
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1071
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Control::2 630896
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Data::2 5624352
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 77112
|
||||
system.ruby.network.routers2.throttle0.link_utilization 4.448659
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 78715
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 79076
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 5667480
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 632608
|
||||
system.ruby.network.routers2.throttle1.link_utilization 4.465188
|
||||
system.ruby.network.routers2.throttle1.msg_count.Control::2 78717
|
||||
system.ruby.network.routers2.throttle1.msg_count.Data::2 78011
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1069
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 629736
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Data::2 5616792
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 76968
|
||||
system.ruby.network.routers3.throttle0.link_utilization 4.467628
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 79054
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::3 79383
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 5691888
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::3 635064
|
||||
system.ruby.network.routers3.throttle1.link_utilization 4.482666
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::2 79057
|
||||
system.ruby.network.routers3.throttle1.msg_count.Data::2 78335
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::4 1051
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Control::2 632456
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Data::2 5640120
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::4 75672
|
||||
system.ruby.network.routers4.throttle0.link_utilization 4.453263
|
||||
system.ruby.network.routers4.throttle0.msg_count.Response_Data::4 78799
|
||||
system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::3 79135
|
||||
system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::4 5673528
|
||||
system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::3 633080
|
||||
system.ruby.network.routers4.throttle1.link_utilization 4.468611
|
||||
system.ruby.network.routers4.throttle1.msg_count.Control::2 78801
|
||||
system.ruby.network.routers4.throttle1.msg_count.Data::2 78061
|
||||
system.ruby.network.routers4.throttle1.msg_count.Response_Data::4 1077
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Control::2 630408
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Data::2 5620392
|
||||
system.ruby.network.routers4.throttle1.msg_bytes.Response_Data::4 77544
|
||||
system.ruby.network.routers5.throttle0.link_utilization 4.448111
|
||||
system.ruby.network.routers5.throttle0.msg_count.Response_Data::4 78709
|
||||
system.ruby.network.routers5.throttle0.msg_count.Writeback_Control::3 79033
|
||||
system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::4 5667048
|
||||
system.ruby.network.routers5.throttle0.msg_bytes.Writeback_Control::3 632264
|
||||
system.ruby.network.routers5.throttle1.link_utilization 4.463075
|
||||
system.ruby.network.routers5.throttle1.msg_count.Control::2 78712
|
||||
system.ruby.network.routers5.throttle1.msg_count.Data::2 77972
|
||||
system.ruby.network.routers5.throttle1.msg_count.Response_Data::4 1067
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Control::2 629696
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Data::2 5613984
|
||||
system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::4 76824
|
||||
system.ruby.network.routers6.throttle0.link_utilization 4.446523
|
||||
system.ruby.network.routers6.throttle0.msg_count.Response_Data::4 78679
|
||||
system.ruby.network.routers6.throttle0.msg_count.Writeback_Control::3 79022
|
||||
system.ruby.network.routers6.throttle0.msg_bytes.Response_Data::4 5664888
|
||||
system.ruby.network.routers6.throttle0.msg_bytes.Writeback_Control::3 632176
|
||||
system.ruby.network.routers6.throttle1.link_utilization 4.462245
|
||||
system.ruby.network.routers6.throttle1.msg_count.Control::2 78682
|
||||
system.ruby.network.routers6.throttle1.msg_count.Data::2 77916
|
||||
system.ruby.network.routers6.throttle1.msg_count.Response_Data::4 1110
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Control::2 629456
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Data::2 5609952
|
||||
system.ruby.network.routers6.throttle1.msg_bytes.Response_Data::4 79920
|
||||
system.ruby.network.routers7.throttle0.link_utilization 4.471854
|
||||
system.ruby.network.routers7.throttle0.msg_count.Response_Data::4 79130
|
||||
system.ruby.network.routers7.throttle0.msg_count.Writeback_Control::3 79450
|
||||
system.ruby.network.routers7.throttle0.msg_bytes.Response_Data::4 5697360
|
||||
system.ruby.network.routers7.throttle0.msg_bytes.Writeback_Control::3 635600
|
||||
system.ruby.network.routers7.throttle1.link_utilization 4.486394
|
||||
system.ruby.network.routers7.throttle1.msg_count.Control::2 79132
|
||||
system.ruby.network.routers7.throttle1.msg_count.Data::2 78429
|
||||
system.ruby.network.routers7.throttle1.msg_count.Response_Data::4 1022
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Control::2 633056
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Data::2 5646888
|
||||
system.ruby.network.routers7.throttle1.msg_bytes.Response_Data::4 73584
|
||||
system.ruby.network.routers8.throttle0.link_utilization 35.341967
|
||||
system.ruby.network.routers8.throttle0.msg_count.Control::2 630869
|
||||
system.ruby.network.routers8.throttle0.msg_count.Data::2 625049
|
||||
system.ruby.network.routers8.throttle0.msg_bytes.Control::2 5046952
|
||||
system.ruby.network.routers8.throttle0.msg_bytes.Data::2 45003528
|
||||
system.ruby.network.routers8.throttle1.link_utilization 35.220468
|
||||
system.ruby.network.routers8.throttle1.msg_count.Response_Data::4 622367
|
||||
system.ruby.network.routers8.throttle1.msg_count.Writeback_Control::3 633506
|
||||
system.ruby.network.routers8.throttle1.msg_bytes.Response_Data::4 44810424
|
||||
system.ruby.network.routers8.throttle1.msg_bytes.Writeback_Control::3 5068048
|
||||
system.ruby.network.routers9.throttle0.link_utilization 4.459092
|
||||
system.ruby.network.routers9.throttle0.msg_count.Response_Data::4 78904
|
||||
system.ruby.network.routers9.throttle0.msg_count.Writeback_Control::3 79222
|
||||
system.ruby.network.routers9.throttle0.msg_bytes.Response_Data::4 5681088
|
||||
system.ruby.network.routers9.throttle0.msg_bytes.Writeback_Control::3 633776
|
||||
system.ruby.network.routers9.throttle1.link_utilization 4.456697
|
||||
system.ruby.network.routers9.throttle1.msg_count.Response_Data::4 78861
|
||||
system.ruby.network.routers9.throttle1.msg_count.Writeback_Control::3 79185
|
||||
system.ruby.network.routers9.throttle1.msg_bytes.Response_Data::4 5677992
|
||||
system.ruby.network.routers9.throttle1.msg_bytes.Writeback_Control::3 633480
|
||||
system.ruby.network.routers9.throttle2.link_utilization 4.448659
|
||||
system.ruby.network.routers9.throttle2.msg_count.Response_Data::4 78715
|
||||
system.ruby.network.routers9.throttle2.msg_count.Writeback_Control::3 79076
|
||||
system.ruby.network.routers9.throttle2.msg_bytes.Response_Data::4 5667480
|
||||
system.ruby.network.routers9.throttle2.msg_bytes.Writeback_Control::3 632608
|
||||
system.ruby.network.routers9.throttle3.link_utilization 4.467628
|
||||
system.ruby.network.routers9.throttle3.msg_count.Response_Data::4 79054
|
||||
system.ruby.network.routers9.throttle3.msg_count.Writeback_Control::3 79383
|
||||
system.ruby.network.routers9.throttle3.msg_bytes.Response_Data::4 5691888
|
||||
system.ruby.network.routers9.throttle3.msg_bytes.Writeback_Control::3 635064
|
||||
system.ruby.network.routers9.throttle4.link_utilization 4.453263
|
||||
system.ruby.network.routers9.throttle4.msg_count.Response_Data::4 78799
|
||||
system.ruby.network.routers9.throttle4.msg_count.Writeback_Control::3 79135
|
||||
system.ruby.network.routers9.throttle4.msg_bytes.Response_Data::4 5673528
|
||||
system.ruby.network.routers9.throttle4.msg_bytes.Writeback_Control::3 633080
|
||||
system.ruby.network.routers9.throttle5.link_utilization 4.448111
|
||||
system.ruby.network.routers9.throttle5.msg_count.Response_Data::4 78709
|
||||
system.ruby.network.routers9.throttle5.msg_count.Writeback_Control::3 79033
|
||||
system.ruby.network.routers9.throttle5.msg_bytes.Response_Data::4 5667048
|
||||
system.ruby.network.routers9.throttle5.msg_bytes.Writeback_Control::3 632264
|
||||
system.ruby.network.routers9.throttle6.link_utilization 4.446523
|
||||
system.ruby.network.routers9.throttle6.msg_count.Response_Data::4 78679
|
||||
system.ruby.network.routers9.throttle6.msg_count.Writeback_Control::3 79022
|
||||
system.ruby.network.routers9.throttle6.msg_bytes.Response_Data::4 5664888
|
||||
system.ruby.network.routers9.throttle6.msg_bytes.Writeback_Control::3 632176
|
||||
system.ruby.network.routers9.throttle7.link_utilization 4.471871
|
||||
system.ruby.network.routers9.throttle7.msg_count.Response_Data::4 79130
|
||||
system.ruby.network.routers9.throttle7.msg_count.Writeback_Control::3 79450
|
||||
system.ruby.network.routers9.throttle7.msg_bytes.Response_Data::4 5697360
|
||||
system.ruby.network.routers9.throttle7.msg_bytes.Writeback_Control::3 635600
|
||||
system.ruby.network.routers9.throttle8.link_utilization 35.341967
|
||||
system.ruby.network.routers9.throttle8.msg_count.Control::2 630869
|
||||
system.ruby.network.routers9.throttle8.msg_count.Data::2 625049
|
||||
system.ruby.network.routers9.throttle8.msg_bytes.Control::2 5046952
|
||||
system.ruby.network.routers9.throttle8.msg_bytes.Data::2 45003528
|
||||
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 617552 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.002021 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 0.103548 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 617290 99.96% 99.96% | 0 0.00% 99.96% | 38 0.01% 99.96% | 0 0.00% 99.96% | 102 0.02% 99.98% | 0 0.00% 99.98% | 106 0.02% 100.00% | 0 0.00% 100.00% | 16 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 617552 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 630851 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.002302 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 0.111910 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 630553 99.95% 99.95% | 0 0.00% 99.95% | 42 0.01% 99.96% | 0 0.00% 99.96% | 109 0.02% 99.98% | 0 0.00% 99.98% | 122 0.02% 100.00% | 0 0.00% 100.00% | 25 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 630851 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 4 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 39 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 620135 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.026309 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 0.408237 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 617823 99.63% 99.63% | 1409 0.23% 99.85% | 881 0.14% 100.00% | 6 0.00% 100.00% | 12 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 620135 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 633506 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.027049 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 0.412821 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 631057 99.61% 99.61% | 1512 0.24% 99.85% | 915 0.14% 100.00% | 5 0.00% 100.00% | 13 0.00% 100.00% | 2 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 633506 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 512
|
||||
system.ruby.LD.latency_hist::max_bucket 5119
|
||||
system.ruby.LD.latency_hist::samples 401489
|
||||
system.ruby.LD.latency_hist::mean 1796.245110
|
||||
system.ruby.LD.latency_hist::gmean 1749.779554
|
||||
system.ruby.LD.latency_hist::stdev 410.866792
|
||||
system.ruby.LD.latency_hist | 31 0.01% 0.01% | 5545 1.38% 1.39% | 105136 26.19% 27.58% | 190357 47.41% 74.99% | 82770 20.62% 95.60% | 15751 3.92% 99.53% | 1714 0.43% 99.95% | 157 0.04% 99.99% | 27 0.01% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 401489
|
||||
system.ruby.LD.latency_hist::samples 405837
|
||||
system.ruby.LD.latency_hist::mean 1795.827911
|
||||
system.ruby.LD.latency_hist::gmean 1749.100087
|
||||
system.ruby.LD.latency_hist::stdev 411.882283
|
||||
system.ruby.LD.latency_hist | 28 0.01% 0.01% | 5711 1.41% 1.41% | 106493 26.24% 27.65% | 191622 47.22% 74.87% | 84296 20.77% 95.64% | 15709 3.87% 99.51% | 1790 0.44% 99.95% | 171 0.04% 100.00% | 14 0.00% 100.00% | 3 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 405837
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 512
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.miss_latency_hist::samples 401489
|
||||
system.ruby.LD.miss_latency_hist::mean 1796.245110
|
||||
system.ruby.LD.miss_latency_hist::gmean 1749.779554
|
||||
system.ruby.LD.miss_latency_hist::stdev 410.866792
|
||||
system.ruby.LD.miss_latency_hist | 31 0.01% 0.01% | 5545 1.38% 1.39% | 105136 26.19% 27.58% | 190357 47.41% 74.99% | 82770 20.62% 95.60% | 15751 3.92% 99.53% | 1714 0.43% 99.95% | 157 0.04% 99.99% | 27 0.01% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 401489
|
||||
system.ruby.LD.miss_latency_hist::samples 405837
|
||||
system.ruby.LD.miss_latency_hist::mean 1795.827911
|
||||
system.ruby.LD.miss_latency_hist::gmean 1749.100087
|
||||
system.ruby.LD.miss_latency_hist::stdev 411.882283
|
||||
system.ruby.LD.miss_latency_hist | 28 0.01% 0.01% | 5711 1.41% 1.41% | 106493 26.24% 27.65% | 191622 47.22% 74.87% | 84296 20.77% 95.64% | 15709 3.87% 99.51% | 1790 0.44% 99.95% | 171 0.04% 100.00% | 14 0.00% 100.00% | 3 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 405837
|
||||
system.ruby.ST.latency_hist::bucket_size 512
|
||||
system.ruby.ST.latency_hist::max_bucket 5119
|
||||
system.ruby.ST.latency_hist::samples 216063
|
||||
system.ruby.ST.latency_hist::mean 1794.884353
|
||||
system.ruby.ST.latency_hist::gmean 1748.377616
|
||||
system.ruby.ST.latency_hist::stdev 411.177879
|
||||
system.ruby.ST.latency_hist | 18 0.01% 0.01% | 2976 1.38% 1.39% | 56720 26.25% 27.64% | 102584 47.48% 75.12% | 44280 20.49% 95.61% | 8413 3.89% 99.50% | 955 0.44% 99.95% | 101 0.05% 99.99% | 15 0.01% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 216063
|
||||
system.ruby.ST.latency_hist::samples 225014
|
||||
system.ruby.ST.latency_hist::mean 1795.524452
|
||||
system.ruby.ST.latency_hist::gmean 1748.632095
|
||||
system.ruby.ST.latency_hist::stdev 412.626104
|
||||
system.ruby.ST.latency_hist | 21 0.01% 0.01% | 3203 1.42% 1.43% | 59194 26.31% 27.74% | 106161 47.18% 74.92% | 46441 20.64% 95.56% | 8899 3.95% 99.51% | 990 0.44% 99.95% | 94 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 225014
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 512
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 5119
|
||||
system.ruby.ST.miss_latency_hist::samples 216063
|
||||
system.ruby.ST.miss_latency_hist::mean 1794.884353
|
||||
system.ruby.ST.miss_latency_hist::gmean 1748.377616
|
||||
system.ruby.ST.miss_latency_hist::stdev 411.177879
|
||||
system.ruby.ST.miss_latency_hist | 18 0.01% 0.01% | 2976 1.38% 1.39% | 56720 26.25% 27.64% | 102584 47.48% 75.12% | 44280 20.49% 95.61% | 8413 3.89% 99.50% | 955 0.44% 99.95% | 101 0.05% 99.99% | 15 0.01% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 216063
|
||||
system.ruby.ST.miss_latency_hist::samples 225014
|
||||
system.ruby.ST.miss_latency_hist::mean 1795.524452
|
||||
system.ruby.ST.miss_latency_hist::gmean 1748.632095
|
||||
system.ruby.ST.miss_latency_hist::stdev 412.626104
|
||||
system.ruby.ST.miss_latency_hist | 21 0.01% 0.01% | 3203 1.42% 1.43% | 59194 26.31% 27.74% | 106161 47.18% 74.92% | 46441 20.64% 95.56% | 8899 3.95% 99.51% | 990 0.44% 99.95% | 94 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 225014
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::samples 8208
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::mean 1692.829678
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::gmean 1644.794246
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::stdev 406.296234
|
||||
system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 237 2.89% 2.89% | 2860 34.84% 37.73% | 3603 43.90% 81.63% | 1287 15.68% 97.31% | 196 2.39% 99.70% | 22 0.27% 99.96% | 3 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::total 8208
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::samples 8485
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::mean 1687.011432
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::gmean 1638.183403
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::stdev 410.098641
|
||||
system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 266 3.13% 3.13% | 3055 36.00% 39.14% | 3618 42.64% 81.78% | 1298 15.30% 97.08% | 223 2.63% 99.71% | 23 0.27% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.L1Cache.miss_mach_latency_hist::total 8485
|
||||
system.ruby.Directory.miss_mach_latency_hist::bucket_size 512
|
||||
system.ruby.Directory.miss_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 609344
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 1797.155638
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 1750.740893
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 410.862833
|
||||
system.ruby.Directory.miss_mach_latency_hist | 49 0.01% 0.01% | 8284 1.36% 1.37% | 158996 26.09% 27.46% | 289338 47.48% 74.94% | 125763 20.64% 95.58% | 23968 3.93% 99.52% | 2647 0.43% 99.95% | 255 0.04% 99.99% | 42 0.01% 100.00% | 2 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 609344
|
||||
system.ruby.Directory.miss_mach_latency_hist::samples 622366
|
||||
system.ruby.Directory.miss_mach_latency_hist::mean 1797.201741
|
||||
system.ruby.Directory.miss_mach_latency_hist::gmean 1750.493671
|
||||
system.ruby.Directory.miss_mach_latency_hist::stdev 411.977479
|
||||
system.ruby.Directory.miss_mach_latency_hist | 49 0.01% 0.01% | 8648 1.39% 1.40% | 162632 26.13% 27.53% | 294165 47.27% 74.79% | 129439 20.80% 95.59% | 24385 3.92% 99.51% | 2757 0.44% 99.95% | 263 0.04% 100.00% | 24 0.00% 100.00% | 4 0.00% 100.00%
|
||||
system.ruby.Directory.miss_mach_latency_hist::total 622366
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 7
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 7
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::samples 4
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.issue_to_initial_request::total 4
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward::max_bucket 9
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 7
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 7
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward::samples 4
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.initial_to_forward::total 4
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::bucket_size 1
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::max_bucket 9
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 7
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 7 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 7
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 32
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 319
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 7
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 113.714286
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 104.188552
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 50.582323
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 1 14.29% 14.29% | 3 42.86% 57.14% | 0 0.00% 57.14% | 0 0.00% 57.14% | 3 42.86% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 7
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::samples 4
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.forward_to_first_response::total 4
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 16
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 159
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 4
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75.250000
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 73.906370
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev 17.211914
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 2 50.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 4
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5357
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1694.452679
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1647.221011
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 402.824830
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 154 2.87% 2.87% | 1856 34.65% 37.52% | 2366 44.17% 81.69% | 844 15.76% 97.44% | 121 2.26% 99.70% | 14 0.26% 99.96% | 2 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5357
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 5527
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1686.068572
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1637.388551
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::stdev 409.754972
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 173 3.13% 3.13% | 1989 35.99% 39.12% | 2361 42.72% 81.83% | 838 15.16% 97.00% | 151 2.73% 99.73% | 14 0.25% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 5527
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 396132
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1797.621677
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1751.209372
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 410.802147
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 31 0.01% 0.01% | 5391 1.36% 1.37% | 103280 26.07% 27.44% | 187991 47.46% 74.90% | 81926 20.68% 95.58% | 15630 3.95% 99.52% | 1700 0.43% 99.95% | 155 0.04% 99.99% | 27 0.01% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 396132
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 400310
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 1797.343336
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 1750.694650
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 411.707345
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist | 28 0.01% 0.01% | 5538 1.38% 1.39% | 104504 26.11% 27.50% | 189261 47.28% 74.77% | 83458 20.85% 95.62% | 15558 3.89% 99.51% | 1776 0.44% 99.95% | 170 0.04% 100.00% | 14 0.00% 100.00% | 3 0.00% 100.00%
|
||||
system.ruby.LD.Directory.miss_type_mach_latency_hist::total 400310
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2851
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1689.780077
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1640.244046
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 412.793948
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 83 2.91% 2.91% | 1004 35.22% 38.13% | 1237 43.39% 81.52% | 443 15.54% 97.05% | 75 2.63% 99.68% | 8 0.28% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2851
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 2958
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1688.773158
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1639.669612
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 410.803541
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 93 3.14% 3.14% | 1066 36.04% 39.18% | 1257 42.49% 81.68% | 460 15.55% 97.23% | 72 2.43% 99.66% | 9 0.30% 99.97% | 1 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 2958
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 512
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 5119
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 213212
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1796.289773
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1749.870827
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 410.975121
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 18 0.01% 0.01% | 2893 1.36% 1.37% | 55716 26.13% 27.50% | 101347 47.53% 75.03% | 43837 20.56% 95.59% | 8338 3.91% 99.50% | 947 0.44% 99.95% | 100 0.05% 99.99% | 15 0.01% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 213212
|
||||
system.ruby.L1Cache_Controller.Load | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50037 12.46% 37.53% | 49672 12.37% 49.90% | 50004 12.45% 62.35% | 50305 12.53% 74.88% | 50279 12.52% 87.40% | 50578 12.60% 100.00%
|
||||
system.ruby.L1Cache_Controller.Load::total 401503
|
||||
system.ruby.L1Cache_Controller.Store | 27007 12.50% 12.50% | 26935 12.47% 24.96% | 26787 12.40% 37.36% | 27153 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.53% 75.11% | 27075 12.53% 87.64% | 26703 12.36% 100.00%
|
||||
system.ruby.L1Cache_Controller.Store::total 216071
|
||||
system.ruby.L1Cache_Controller.Data | 77375 12.53% 12.53% | 77192 12.50% 25.03% | 76821 12.44% 37.47% | 76821 12.44% 49.91% | 77329 12.52% 62.43% | 77385 12.53% 74.96% | 77352 12.53% 87.49% | 77277 12.51% 100.00%
|
||||
system.ruby.L1Cache_Controller.Data::total 617552
|
||||
system.ruby.L1Cache_Controller.Fwd_GETX | 1048 12.77% 12.77% | 1042 12.69% 25.46% | 1040 12.67% 38.13% | 1065 12.98% 51.11% | 995 12.12% 63.23% | 1001 12.20% 75.43% | 998 12.16% 87.59% | 1019 12.41% 100.00%
|
||||
system.ruby.L1Cache_Controller.Fwd_GETX::total 8208
|
||||
system.ruby.L1Cache_Controller.Replacement | 77373 12.53% 12.53% | 77189 12.50% 25.03% | 76820 12.44% 37.47% | 76821 12.44% 49.91% | 77327 12.52% 62.43% | 77385 12.53% 74.96% | 77350 12.53% 87.49% | 77277 12.51% 100.00%
|
||||
system.ruby.L1Cache_Controller.Replacement::total 617542
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack | 76323 12.53% 12.53% | 76144 12.50% 25.02% | 75775 12.44% 37.46% | 75751 12.43% 49.89% | 76330 12.53% 62.42% | 76378 12.54% 74.95% | 76350 12.53% 87.49% | 76253 12.51% 100.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack::total 609304
|
||||
system.ruby.L1Cache_Controller.Writeback_Nack | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Nack::total 2623
|
||||
system.ruby.L1Cache_Controller.I.Load | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50037 12.46% 37.53% | 49672 12.37% 49.90% | 50004 12.45% 62.35% | 50305 12.53% 74.88% | 50279 12.52% 87.40% | 50578 12.60% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Load::total 401503
|
||||
system.ruby.L1Cache_Controller.I.Store | 27007 12.50% 12.50% | 26935 12.47% 24.96% | 26787 12.40% 37.36% | 27153 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.53% 75.11% | 27075 12.53% 87.64% | 26703 12.36% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Store::total 216071
|
||||
system.ruby.L1Cache_Controller.I.Replacement | 706 12.64% 12.64% | 720 12.89% 25.53% | 716 12.82% 38.35% | 724 12.96% 51.32% | 668 11.96% 63.28% | 657 11.76% 75.04% | 688 12.32% 87.36% | 706 12.64% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Replacement::total 5585
|
||||
system.ruby.L1Cache_Controller.II.Writeback_Nack | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00%
|
||||
system.ruby.L1Cache_Controller.II.Writeback_Nack::total 2623
|
||||
system.ruby.L1Cache_Controller.M.Fwd_GETX | 706 12.64% 12.64% | 720 12.89% 25.53% | 716 12.82% 38.35% | 724 12.96% 51.32% | 668 11.96% 63.28% | 657 11.76% 75.04% | 688 12.32% 87.36% | 706 12.64% 100.00%
|
||||
system.ruby.L1Cache_Controller.M.Fwd_GETX::total 5585
|
||||
system.ruby.L1Cache_Controller.M.Replacement | 76667 12.53% 12.53% | 76469 12.50% 25.02% | 76104 12.44% 37.46% | 76097 12.44% 49.90% | 76659 12.53% 62.42% | 76728 12.54% 74.96% | 76662 12.53% 87.49% | 76571 12.51% 100.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement::total 611957
|
||||
system.ruby.L1Cache_Controller.MI.Fwd_GETX | 342 13.04% 13.04% | 322 12.28% 25.31% | 324 12.35% 37.67% | 341 13.00% 50.67% | 327 12.47% 63.13% | 344 13.11% 76.25% | 310 11.82% 88.07% | 313 11.93% 100.00%
|
||||
system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 2623
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack | 76323 12.53% 12.53% | 76144 12.50% 25.02% | 75775 12.44% 37.46% | 75751 12.43% 49.89% | 76330 12.53% 62.42% | 76378 12.54% 74.95% | 76350 12.53% 87.49% | 76253 12.51% 100.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 609304
|
||||
system.ruby.L1Cache_Controller.IS.Data | 50370 12.55% 12.55% | 50258 12.52% 25.06% | 50035 12.46% 37.53% | 49669 12.37% 49.90% | 50002 12.45% 62.35% | 50301 12.53% 74.88% | 50278 12.52% 87.40% | 50576 12.60% 100.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data::total 401489
|
||||
system.ruby.L1Cache_Controller.IM.Data | 27005 12.50% 12.50% | 26934 12.47% 24.96% | 26786 12.40% 37.36% | 27152 12.57% 49.93% | 27327 12.65% 62.58% | 27084 12.54% 75.11% | 27074 12.53% 87.64% | 26701 12.36% 100.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data::total 216063
|
||||
system.ruby.Directory_Controller.GETX 791175 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 609324 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX_NotOwner 2623 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 609345 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 609304 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 609354 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.GETX 8208 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 609324 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX_NotOwner 2623 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.GETX 65257 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 609345 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.GETX 108356 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 609304 0.00% 0.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 222056
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 1796.946482
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 1750.131417
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 412.464819
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist | 21 0.01% 0.01% | 3110 1.40% 1.41% | 58128 26.18% 27.59% | 104904 47.24% 74.83% | 45981 20.71% 95.54% | 8827 3.98% 99.51% | 981 0.44% 99.95% | 93 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00%
|
||||
system.ruby.ST.Directory.miss_type_mach_latency_hist::total 222056
|
||||
system.ruby.L1Cache_Controller.Load | 50822 12.52% 12.52% | 50930 12.55% 25.07% | 50579 12.46% 37.53% | 50992 12.56% 50.10% | 50750 12.50% 62.60% | 50396 12.42% 75.02% | 50785 12.51% 87.53% | 50593 12.47% 100.00%
|
||||
system.ruby.L1Cache_Controller.Load::total 405847
|
||||
system.ruby.L1Cache_Controller.Store | 28084 12.48% 12.48% | 27932 12.41% 24.89% | 28138 12.50% 37.40% | 28065 12.47% 49.87% | 28051 12.47% 62.34% | 28316 12.58% 74.92% | 27897 12.40% 87.32% | 28539 12.68% 100.00%
|
||||
system.ruby.L1Cache_Controller.Store::total 225022
|
||||
system.ruby.L1Cache_Controller.Data | 78904 12.51% 12.51% | 78861 12.50% 25.01% | 78715 12.48% 37.49% | 79054 12.53% 50.02% | 78799 12.49% 62.51% | 78709 12.48% 74.98% | 78679 12.47% 87.46% | 79130 12.54% 100.00%
|
||||
system.ruby.L1Cache_Controller.Data::total 630851
|
||||
system.ruby.L1Cache_Controller.Fwd_GETX | 1018 12.00% 12.00% | 1071 12.62% 24.62% | 1069 12.60% 37.22% | 1051 12.39% 49.61% | 1077 12.69% 62.30% | 1067 12.58% 74.87% | 1110 13.08% 87.96% | 1022 12.04% 100.00%
|
||||
system.ruby.L1Cache_Controller.Fwd_GETX::total 8485
|
||||
system.ruby.L1Cache_Controller.Replacement | 78902 12.51% 12.51% | 78858 12.50% 25.01% | 78713 12.48% 37.49% | 79053 12.53% 50.02% | 78797 12.49% 62.51% | 78708 12.48% 74.98% | 78678 12.47% 87.46% | 79128 12.54% 100.00%
|
||||
system.ruby.L1Cache_Controller.Replacement::total 630837
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack | 77879 12.51% 12.51% | 77785 12.50% 25.01% | 77640 12.48% 37.49% | 77999 12.53% 50.02% | 77717 12.49% 62.51% | 77635 12.48% 74.99% | 77564 12.46% 87.45% | 78105 12.55% 100.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack::total 622324
|
||||
system.ruby.L1Cache_Controller.Writeback_Nack | 325 12.05% 12.05% | 329 12.20% 24.25% | 367 13.61% 37.86% | 333 12.35% 50.20% | 341 12.64% 62.85% | 331 12.27% 75.12% | 348 12.90% 88.02% | 323 11.98% 100.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Nack::total 2697
|
||||
system.ruby.L1Cache_Controller.I.Load | 50822 12.52% 12.52% | 50930 12.55% 25.07% | 50579 12.46% 37.53% | 50992 12.56% 50.10% | 50750 12.50% 62.60% | 50396 12.42% 75.02% | 50785 12.51% 87.53% | 50593 12.47% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Load::total 405847
|
||||
system.ruby.L1Cache_Controller.I.Store | 28084 12.48% 12.48% | 27932 12.41% 24.89% | 28138 12.50% 37.40% | 28065 12.47% 49.87% | 28051 12.47% 62.34% | 28316 12.58% 74.92% | 27897 12.40% 87.32% | 28539 12.68% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Store::total 225022
|
||||
system.ruby.L1Cache_Controller.I.Replacement | 693 11.97% 11.97% | 742 12.82% 24.79% | 702 12.13% 36.92% | 718 12.40% 49.33% | 736 12.72% 62.04% | 736 12.72% 74.76% | 762 13.17% 87.92% | 699 12.08% 100.00%
|
||||
system.ruby.L1Cache_Controller.I.Replacement::total 5788
|
||||
system.ruby.L1Cache_Controller.II.Writeback_Nack | 325 12.05% 12.05% | 329 12.20% 24.25% | 367 13.61% 37.86% | 333 12.35% 50.20% | 341 12.64% 62.85% | 331 12.27% 75.12% | 348 12.90% 88.02% | 323 11.98% 100.00%
|
||||
system.ruby.L1Cache_Controller.II.Writeback_Nack::total 2697
|
||||
system.ruby.L1Cache_Controller.M.Fwd_GETX | 693 11.97% 11.97% | 742 12.82% 24.79% | 702 12.13% 36.92% | 718 12.40% 49.33% | 736 12.72% 62.04% | 736 12.72% 74.76% | 762 13.17% 87.92% | 699 12.08% 100.00%
|
||||
system.ruby.L1Cache_Controller.M.Fwd_GETX::total 5788
|
||||
system.ruby.L1Cache_Controller.M.Replacement | 78209 12.51% 12.51% | 78116 12.50% 25.01% | 78011 12.48% 37.49% | 78335 12.53% 50.02% | 78061 12.49% 62.51% | 77972 12.47% 74.99% | 77916 12.47% 87.45% | 78429 12.55% 100.00%
|
||||
system.ruby.L1Cache_Controller.M.Replacement::total 625049
|
||||
system.ruby.L1Cache_Controller.MI.Fwd_GETX | 325 12.05% 12.05% | 329 12.20% 24.25% | 367 13.61% 37.86% | 333 12.35% 50.20% | 341 12.64% 62.85% | 331 12.27% 75.12% | 348 12.90% 88.02% | 323 11.98% 100.00%
|
||||
system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 2697
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack | 77879 12.51% 12.51% | 77785 12.50% 25.01% | 77640 12.48% 37.49% | 77999 12.53% 50.02% | 77717 12.49% 62.51% | 77635 12.48% 74.99% | 77564 12.46% 87.45% | 78105 12.55% 100.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack::total 622324
|
||||
system.ruby.L1Cache_Controller.IS.Data | 50821 12.52% 12.52% | 50929 12.55% 25.07% | 50577 12.46% 37.53% | 50990 12.56% 50.10% | 50750 12.51% 62.60% | 50395 12.42% 75.02% | 50783 12.51% 87.53% | 50592 12.47% 100.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data::total 405837
|
||||
system.ruby.L1Cache_Controller.IM.Data | 28083 12.48% 12.48% | 27932 12.41% 24.89% | 28138 12.50% 37.40% | 28064 12.47% 49.87% | 28049 12.47% 62.34% | 28314 12.58% 74.92% | 27896 12.40% 87.32% | 28538 12.68% 100.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data::total 225014
|
||||
system.ruby.Directory_Controller.GETX 808444 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 622352 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX_NotOwner 2697 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 622367 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 622324 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 622384 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.GETX 8485 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 622352 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX_NotOwner 2697 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.GETX 68392 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 622367 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.GETX 109183 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 622324 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,60 +1,60 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000312 # Number of seconds simulated
|
||||
sim_ticks 312261 # Number of ticks simulated
|
||||
final_tick 312261 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000328 # Number of seconds simulated
|
||||
sim_ticks 327571 # Number of ticks simulated
|
||||
final_tick 327571 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 1203947 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 170440 # Number of bytes of host memory used
|
||||
host_tick_rate 1251967 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 128368 # Number of bytes of host memory used
|
||||
host_seconds 0.26 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.delayHist::bucket_size 512 # delay histogram for all message
|
||||
system.ruby.delayHist::max_bucket 5119 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 6975 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 57.310251 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 258.377513 # delay histogram for all message
|
||||
system.ruby.delayHist | 6687 95.87% 95.87% | 165 2.37% 98.24% | 67 0.96% 99.20% | 29 0.42% 99.61% | 15 0.22% 99.83% | 8 0.11% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 6975 # delay histogram for all message
|
||||
system.ruby.delayHist::samples 7183 # delay histogram for all message
|
||||
system.ruby.delayHist::mean 55.693443 # delay histogram for all message
|
||||
system.ruby.delayHist::stdev 252.452700 # delay histogram for all message
|
||||
system.ruby.delayHist | 6908 96.17% 96.17% | 159 2.21% 98.39% | 57 0.79% 99.18% | 31 0.43% 99.61% | 18 0.25% 99.86% | 9 0.13% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% # delay histogram for all message
|
||||
system.ruby.delayHist::total 7183 # delay histogram for all message
|
||||
system.ruby.outstanding_req_hist::bucket_size 2
|
||||
system.ruby.outstanding_req_hist::max_bucket 19
|
||||
system.ruby.outstanding_req_hist::samples 983
|
||||
system.ruby.outstanding_req_hist::mean 15.827060
|
||||
system.ruby.outstanding_req_hist::gmean 15.727011
|
||||
system.ruby.outstanding_req_hist::stdev 1.133008
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.31% | 2 0.20% 0.51% | 2 0.20% 0.71% | 2 0.20% 0.92% | 2 0.20% 1.12% | 2 0.20% 1.32% | 52 5.29% 6.61% | 918 93.39% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 983
|
||||
system.ruby.outstanding_req_hist::samples 1017
|
||||
system.ruby.outstanding_req_hist::mean 15.830875
|
||||
system.ruby.outstanding_req_hist::gmean 15.734065
|
||||
system.ruby.outstanding_req_hist::stdev 1.114909
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.29% | 2 0.20% 0.49% | 2 0.20% 0.69% | 2 0.20% 0.88% | 2 0.20% 1.08% | 2 0.20% 1.28% | 54 5.31% 6.59% | 950 93.41% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 1017
|
||||
system.ruby.latency_hist::bucket_size 1024
|
||||
system.ruby.latency_hist::max_bucket 10239
|
||||
system.ruby.latency_hist::samples 968
|
||||
system.ruby.latency_hist::mean 5101.012397
|
||||
system.ruby.latency_hist::gmean 2832.118198
|
||||
system.ruby.latency_hist::stdev 2084.563420
|
||||
system.ruby.latency_hist | 125 12.91% 12.91% | 22 2.27% 15.19% | 2 0.21% 15.39% | 4 0.41% 15.81% | 57 5.89% 21.69% | 468 48.35% 70.04% | 263 27.17% 97.21% | 27 2.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 968
|
||||
system.ruby.latency_hist::samples 1002
|
||||
system.ruby.latency_hist::mean 5171.353293
|
||||
system.ruby.latency_hist::gmean 2828.922262
|
||||
system.ruby.latency_hist::stdev 2096.025855
|
||||
system.ruby.latency_hist | 135 13.47% 13.47% | 12 1.20% 14.67% | 4 0.40% 15.07% | 4 0.40% 15.47% | 30 2.99% 18.46% | 460 45.91% 64.37% | 320 31.94% 96.31% | 37 3.69% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 1002
|
||||
system.ruby.hit_latency_hist::bucket_size 16
|
||||
system.ruby.hit_latency_hist::max_bucket 159
|
||||
system.ruby.hit_latency_hist::samples 74
|
||||
system.ruby.hit_latency_hist::mean 11.527027
|
||||
system.ruby.hit_latency_hist::gmean 3.324632
|
||||
system.ruby.hit_latency_hist::stdev 29.929242
|
||||
system.ruby.hit_latency_hist | 68 91.89% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 0 0.00% 91.89% | 2 2.70% 94.59% | 4 5.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 74
|
||||
system.ruby.hit_latency_hist::samples 77
|
||||
system.ruby.hit_latency_hist::mean 9.597403
|
||||
system.ruby.hit_latency_hist::gmean 2.761367
|
||||
system.ruby.hit_latency_hist::stdev 27.303489
|
||||
system.ruby.hit_latency_hist | 72 93.51% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 0 0.00% 93.51% | 2 2.60% 96.10% | 3 3.90% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 77
|
||||
system.ruby.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.miss_latency_hist::samples 894
|
||||
system.ruby.miss_latency_hist::mean 5522.289709
|
||||
system.ruby.miss_latency_hist::gmean 4950.736161
|
||||
system.ruby.miss_latency_hist::stdev 1543.133800
|
||||
system.ruby.miss_latency_hist | 51 5.70% 5.70% | 22 2.46% 8.17% | 2 0.22% 8.39% | 4 0.45% 8.84% | 57 6.38% 15.21% | 468 52.35% 67.56% | 263 29.42% 96.98% | 27 3.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 894
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 74 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 839 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 913 # Number of cache demand accesses
|
||||
system.ruby.miss_latency_hist::samples 925
|
||||
system.ruby.miss_latency_hist::mean 5601.034595
|
||||
system.ruby.miss_latency_hist::gmean 5037.610012
|
||||
system.ruby.miss_latency_hist::stdev 1534.352398
|
||||
system.ruby.miss_latency_hist | 58 6.27% 6.27% | 12 1.30% 7.57% | 4 0.43% 8.00% | 4 0.43% 8.43% | 30 3.24% 11.68% | 460 49.73% 61.41% | 320 34.59% 96.00% | 37 4.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 925
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 77 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 881 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 958 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 57 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 57 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 46 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 46 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed
|
||||
system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching
|
||||
system.ruby.l1_cntrl0.prefetcher.prefetches_requested 0 # number of prefetch requests made
|
||||
@@ -64,355 +64,355 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
|
||||
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
|
||||
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
|
||||
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 5 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 80 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 6 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 1 # Number of times a load aliased with a pending load
|
||||
system.ruby.network.routers0.percent_links_utilized 1.779361
|
||||
system.ruby.network.routers0.msg_count.Control::0 896
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 559
|
||||
system.ruby.network.routers0.msg_count.Response_Data::1 894
|
||||
system.ruby.network.routers0.msg_count.Response_Control::1 812
|
||||
system.ruby.network.routers0.msg_count.Response_Control::2 837
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::0 726
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::1 501
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 32
|
||||
system.ruby.network.routers0.msg_bytes.Control::0 7168
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::2 4472
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::1 64368
|
||||
system.ruby.network.routers0.msg_bytes.Response_Control::1 6496
|
||||
system.ruby.network.routers0.msg_bytes.Response_Control::2 6696
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 52272
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 36072
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 256
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 32 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 864 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 896 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 3.102133
|
||||
system.ruby.network.routers1.msg_count.Control::0 1759
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 559
|
||||
system.ruby.network.routers1.msg_count.Response_Data::1 2529
|
||||
system.ruby.network.routers1.msg_count.Response_Control::1 1756
|
||||
system.ruby.network.routers1.msg_count.Response_Control::2 837
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::0 726
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::1 501
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 32
|
||||
system.ruby.network.routers1.msg_bytes.Control::0 14072
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 4472
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::1 182088
|
||||
system.ruby.network.routers1.msg_bytes.Response_Control::1 14048
|
||||
system.ruby.network.routers1.msg_bytes.Response_Control::2 6696
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 52272
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 36072
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 256
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 6 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 110 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 10 # Number of times a load aliased with a pending store
|
||||
system.ruby.network.routers0.percent_links_utilized 1.749086
|
||||
system.ruby.network.routers0.msg_count.Control::0 925
|
||||
system.ruby.network.routers0.msg_count.Request_Control::2 563
|
||||
system.ruby.network.routers0.msg_count.Response_Data::1 925
|
||||
system.ruby.network.routers0.msg_count.Response_Control::1 827
|
||||
system.ruby.network.routers0.msg_count.Response_Control::2 877
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::0 742
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::1 520
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 43
|
||||
system.ruby.network.routers0.msg_bytes.Control::0 7400
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::2 4504
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::1 66600
|
||||
system.ruby.network.routers0.msg_bytes.Response_Control::1 6616
|
||||
system.ruby.network.routers0.msg_bytes.Response_Control::2 7016
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 53424
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 37440
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 344
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 41 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 884 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 925 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 3.043386
|
||||
system.ruby.network.routers1.msg_count.Control::0 1809
|
||||
system.ruby.network.routers1.msg_count.Request_Control::2 563
|
||||
system.ruby.network.routers1.msg_count.Response_Data::1 2604
|
||||
system.ruby.network.routers1.msg_count.Response_Control::1 1791
|
||||
system.ruby.network.routers1.msg_count.Response_Control::2 877
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::0 742
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::1 520
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 43
|
||||
system.ruby.network.routers1.msg_bytes.Control::0 14472
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::2 4504
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::1 187488
|
||||
system.ruby.network.routers1.msg_bytes.Response_Control::1 14328
|
||||
system.ruby.network.routers1.msg_bytes.Response_Control::2 7016
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 53424
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 37440
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 344
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1633 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 863 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 770 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 2168 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 631 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankQ 4 # Delay behind the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 681 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.417024 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 209 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 210 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 102 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 76 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 34 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 41 2.51% 2.51% | 47 2.88% 5.39% | 57 3.49% 8.88% | 77 4.72% 13.59% | 68 4.16% 17.76% | 61 3.74% 21.49% | 66 4.04% 25.54% | 57 3.49% 29.03% | 48 2.94% 31.97% | 40 2.45% 34.42% | 51 3.12% 37.54% | 55 3.37% 40.91% | 46 2.82% 43.72% | 63 3.86% 47.58% | 42 2.57% 50.15% | 41 2.51% 52.66% | 40 2.45% 55.11% | 63 3.86% 58.97% | 38 2.33% 61.30% | 41 2.51% 63.81% | 44 2.69% 66.50% | 54 3.31% 69.81% | 50 3.06% 72.87% | 49 3.00% 75.87% | 56 3.43% 79.30% | 41 2.51% 81.81% | 55 3.37% 85.18% | 35 2.14% 87.32% | 45 2.76% 90.08% | 56 3.43% 93.51% | 51 3.12% 96.63% | 55 3.37% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1633 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 1.321331
|
||||
system.ruby.network.routers2.msg_count.Control::0 863
|
||||
system.ruby.network.routers2.msg_count.Response_Data::1 1633
|
||||
system.ruby.network.routers2.msg_count.Response_Control::1 944
|
||||
system.ruby.network.routers2.msg_bytes.Control::0 6904
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 117576
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 7552
|
||||
system.ruby.network.routers3.percent_links_utilized 2.067608
|
||||
system.ruby.network.routers3.msg_count.Control::0 1759
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 559
|
||||
system.ruby.network.routers3.msg_count.Response_Data::1 2528
|
||||
system.ruby.network.routers3.msg_count.Response_Control::1 1756
|
||||
system.ruby.network.routers3.msg_count.Response_Control::2 837
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::0 726
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::1 501
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 32
|
||||
system.ruby.network.routers3.msg_bytes.Control::0 14072
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::2 4472
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::1 182016
|
||||
system.ruby.network.routers3.msg_bytes.Response_Control::1 14048
|
||||
system.ruby.network.routers3.msg_bytes.Response_Control::2 6696
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 52272
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 36072
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 256
|
||||
system.ruby.network.msg_count.Control 5277
|
||||
system.ruby.network.msg_count.Request_Control 1677
|
||||
system.ruby.network.msg_count.Response_Data 7584
|
||||
system.ruby.network.msg_count.Response_Control 7779
|
||||
system.ruby.network.msg_count.Writeback_Data 3681
|
||||
system.ruby.network.msg_count.Writeback_Control 96
|
||||
system.ruby.network.msg_byte.Control 42216
|
||||
system.ruby.network.msg_byte.Request_Control 13416
|
||||
system.ruby.network.msg_byte.Response_Data 546048
|
||||
system.ruby.network.msg_byte.Response_Control 62232
|
||||
system.ruby.network.msg_byte.Writeback_Data 265032
|
||||
system.ruby.network.msg_byte.Writeback_Control 768
|
||||
system.ruby.network.routers0.throttle0.link_utilization 1.498906
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 559
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 894
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 756
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 4472
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 64368
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6048
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.059815
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 896
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 56
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 837
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 726
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 501
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 32
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7168
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 448
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 6696
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 52272
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 36072
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 256
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.440711
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 896
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 863
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 913
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 837
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 726
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 501
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 32
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7168
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 62136
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7304
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 6696
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 52272
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 36072
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 256
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.763554
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 863
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 559
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1666
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 843
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Control::0 6904
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 4472
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 119952
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6744
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.261765
|
||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 863
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 770
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 87
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 6904
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 55440
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 696
|
||||
system.ruby.network.routers2.throttle1.link_utilization 1.380896
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 863
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 857
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 62136
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 6856
|
||||
system.ruby.network.routers3.throttle0.link_utilization 1.498906
|
||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 559
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 894
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 756
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 4472
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 64368
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6048
|
||||
system.ruby.network.routers3.throttle1.link_utilization 3.440711
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 896
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 863
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 913
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 837
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 726
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 501
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 32
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7168
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 62136
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7304
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 6696
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 52272
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 36072
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 256
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.263206
|
||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 863
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 771
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 87
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Control::0 6904
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 55512
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 696
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1679 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 884 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 795 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 2274 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 511 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 43 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 554 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.329958 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 149 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 180 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 93 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 29 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 59 3.51% 3.51% | 51 3.04% 6.55% | 42 2.50% 9.05% | 102 6.08% 15.13% | 61 3.63% 18.76% | 47 2.80% 21.56% | 70 4.17% 25.73% | 56 3.34% 29.06% | 51 3.04% 32.10% | 62 3.69% 35.80% | 53 3.16% 38.95% | 35 2.08% 41.04% | 65 3.87% 44.91% | 50 2.98% 47.89% | 40 2.38% 50.27% | 53 3.16% 53.42% | 36 2.14% 55.57% | 55 3.28% 58.84% | 66 3.93% 62.78% | 41 2.44% 65.22% | 49 2.92% 68.14% | 43 2.56% 70.70% | 65 3.87% 74.57% | 53 3.16% 77.72% | 50 2.98% 80.70% | 53 3.16% 83.86% | 51 3.04% 86.90% | 48 2.86% 89.76% | 44 2.62% 92.38% | 41 2.44% 94.82% | 41 2.44% 97.26% | 46 2.74% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1679 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 1.294300
|
||||
system.ruby.network.routers2.msg_count.Control::0 884
|
||||
system.ruby.network.routers2.msg_count.Response_Data::1 1679
|
||||
system.ruby.network.routers2.msg_count.Response_Control::1 964
|
||||
system.ruby.network.routers2.msg_bytes.Control::0 7072
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::1 120888
|
||||
system.ruby.network.routers2.msg_bytes.Response_Control::1 7712
|
||||
system.ruby.network.routers3.percent_links_utilized 2.028924
|
||||
system.ruby.network.routers3.msg_count.Control::0 1809
|
||||
system.ruby.network.routers3.msg_count.Request_Control::2 563
|
||||
system.ruby.network.routers3.msg_count.Response_Data::1 2604
|
||||
system.ruby.network.routers3.msg_count.Response_Control::1 1791
|
||||
system.ruby.network.routers3.msg_count.Response_Control::2 877
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::0 742
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::1 520
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 43
|
||||
system.ruby.network.routers3.msg_bytes.Control::0 14472
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::2 4504
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::1 187488
|
||||
system.ruby.network.routers3.msg_bytes.Response_Control::1 14328
|
||||
system.ruby.network.routers3.msg_bytes.Response_Control::2 7016
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 53424
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 37440
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 344
|
||||
system.ruby.network.msg_count.Control 5427
|
||||
system.ruby.network.msg_count.Request_Control 1689
|
||||
system.ruby.network.msg_count.Response_Data 7812
|
||||
system.ruby.network.msg_count.Response_Control 8004
|
||||
system.ruby.network.msg_count.Writeback_Data 3786
|
||||
system.ruby.network.msg_count.Writeback_Control 129
|
||||
system.ruby.network.msg_byte.Control 43416
|
||||
system.ruby.network.msg_byte.Request_Control 13512
|
||||
system.ruby.network.msg_byte.Response_Data 562464
|
||||
system.ruby.network.msg_byte.Response_Control 64032
|
||||
system.ruby.network.msg_byte.Writeback_Data 272592
|
||||
system.ruby.network.msg_byte.Writeback_Control 1032
|
||||
system.ruby.network.routers0.throttle0.link_utilization 1.476321
|
||||
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 563
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 925
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 784
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 4504
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 66600
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 6272
|
||||
system.ruby.network.routers0.throttle1.link_utilization 2.021852
|
||||
system.ruby.network.routers0.throttle1.msg_count.Control::0 925
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 43
|
||||
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 877
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 742
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 520
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 43
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7400
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 344
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 7016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 53424
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 37440
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 344
|
||||
system.ruby.network.routers1.throttle0.link_utilization 3.370414
|
||||
system.ruby.network.routers1.throttle0.msg_count.Control::0 925
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 884
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 922
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Control::2 877
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::0 742
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::1 520
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 43
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Control::0 7400
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::1 63648
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::1 7376
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 7016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 53424
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 37440
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 344
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.716358
|
||||
system.ruby.network.routers1.throttle1.msg_count.Control::0 884
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 563
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1720
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 869
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Control::0 7072
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 4504
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 123840
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 6952
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.240037
|
||||
system.ruby.network.routers2.throttle0.msg_count.Control::0 884
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 795
|
||||
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 85
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 7072
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 57240
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 680
|
||||
system.ruby.network.routers2.throttle1.link_utilization 1.348563
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 884
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 879
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 63648
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 7032
|
||||
system.ruby.network.routers3.throttle0.link_utilization 1.476321
|
||||
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 563
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 925
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 784
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 4504
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 66600
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 6272
|
||||
system.ruby.network.routers3.throttle1.link_utilization 3.370414
|
||||
system.ruby.network.routers3.throttle1.msg_count.Control::0 925
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 884
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 922
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Control::2 877
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::0 742
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::1 520
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 43
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Control::0 7400
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 63648
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 7376
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 7016
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 53424
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 37440
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 344
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.240037
|
||||
system.ruby.network.routers3.throttle2.msg_count.Control::0 884
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 795
|
||||
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 85
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Control::0 7072
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Response_Data::1 57240
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Response_Control::1 680
|
||||
system.ruby.delayVCHist.vnet_0::bucket_size 512 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::max_bucket 5119 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::samples 2489 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::mean 159.486139 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::stdev 413.379625 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0 | 2201 88.43% 88.43% | 165 6.63% 95.06% | 67 2.69% 97.75% | 29 1.17% 98.92% | 15 0.60% 99.52% | 8 0.32% 99.84% | 4 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::total 2489 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::samples 2586 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::mean 153.589327 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::stdev 402.594576 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0 | 2311 89.37% 89.37% | 159 6.15% 95.51% | 57 2.20% 97.72% | 31 1.20% 98.92% | 18 0.70% 99.61% | 9 0.35% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_0::total 2586 # delay histogram for vnet_0
|
||||
system.ruby.delayVCHist.vnet_1::bucket_size 4 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::max_bucket 39 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 3927 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.706901 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 2.143932 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 3546 90.30% 90.30% | 268 6.82% 97.12% | 81 2.06% 99.19% | 28 0.71% 99.90% | 1 0.03% 99.92% | 3 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 3927 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::samples 4034 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::mean 0.709470 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::stdev 2.104009 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1 | 3622 89.79% 89.79% | 315 7.81% 97.60% | 68 1.69% 99.28% | 23 0.57% 99.85% | 5 0.12% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_1::total 4034 # delay histogram for vnet_1
|
||||
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 559 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.003578 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 0.084591 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 558 99.82% 99.82% | 0 0.00% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 559 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::samples 563 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::mean 0.003552 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::stdev 0.084290 # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2 | 562 99.82% 99.82% | 0 0.00% 99.82% | 1 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
|
||||
system.ruby.delayVCHist.vnet_2::total 563 # delay histogram for vnet_2
|
||||
system.ruby.LD.latency_hist::bucket_size 1024
|
||||
system.ruby.LD.latency_hist::max_bucket 10239
|
||||
system.ruby.LD.latency_hist::samples 43
|
||||
system.ruby.LD.latency_hist::mean 5169.837209
|
||||
system.ruby.LD.latency_hist::gmean 2077.331542
|
||||
system.ruby.LD.latency_hist::stdev 2197.240205
|
||||
system.ruby.LD.latency_hist | 6 13.95% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 0 0.00% 13.95% | 2 4.65% 18.60% | 22 51.16% 69.77% | 10 23.26% 93.02% | 3 6.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 43
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 6
|
||||
system.ruby.LD.hit_latency_hist::mean 3.166667
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.086164
|
||||
system.ruby.LD.hit_latency_hist::stdev 0.752773
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 16.67% 16.67% | 3 50.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 6
|
||||
system.ruby.LD.latency_hist::samples 54
|
||||
system.ruby.LD.latency_hist::mean 5695.537037
|
||||
system.ruby.LD.latency_hist::gmean 3661.591532
|
||||
system.ruby.LD.latency_hist::stdev 1733.262348
|
||||
system.ruby.LD.latency_hist | 4 7.41% 7.41% | 0 0.00% 7.41% | 0 0.00% 7.41% | 0 0.00% 7.41% | 3 5.56% 12.96% | 19 35.19% 48.15% | 24 44.44% 92.59% | 4 7.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 54
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 16
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 159
|
||||
system.ruby.LD.hit_latency_hist::samples 4
|
||||
system.ruby.LD.hit_latency_hist::mean 29.500000
|
||||
system.ruby.LD.hit_latency_hist::gmean 6.027587
|
||||
system.ruby.LD.hit_latency_hist::stdev 53.681157
|
||||
system.ruby.LD.hit_latency_hist | 3 75.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 0 0.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 4
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.LD.miss_latency_hist::samples 37
|
||||
system.ruby.LD.miss_latency_hist::mean 6007.675676
|
||||
system.ruby.LD.miss_latency_hist::gmean 5971.927068
|
||||
system.ruby.LD.miss_latency_hist::stdev 679.672881
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 5.41% 5.41% | 22 59.46% 64.86% | 10 27.03% 91.89% | 3 8.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 37
|
||||
system.ruby.LD.miss_latency_hist::samples 50
|
||||
system.ruby.LD.miss_latency_hist::mean 6148.820000
|
||||
system.ruby.LD.miss_latency_hist::gmean 6114.374114
|
||||
system.ruby.LD.miss_latency_hist::stdev 647.202668
|
||||
system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 6.00% 6.00% | 19 38.00% 44.00% | 24 48.00% 92.00% | 4 8.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 50
|
||||
system.ruby.ST.latency_hist::bucket_size 1024
|
||||
system.ruby.ST.latency_hist::max_bucket 10239
|
||||
system.ruby.ST.latency_hist::samples 868
|
||||
system.ruby.ST.latency_hist::mean 5376.413594
|
||||
system.ruby.ST.latency_hist::gmean 3136.848535
|
||||
system.ruby.ST.latency_hist::stdev 1827.946779
|
||||
system.ruby.ST.latency_hist | 82 9.45% 9.45% | 2 0.23% 9.68% | 2 0.23% 9.91% | 4 0.46% 10.37% | 55 6.34% 16.71% | 446 51.38% 68.09% | 253 29.15% 97.24% | 24 2.76% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 868
|
||||
system.ruby.ST.latency_hist::samples 902
|
||||
system.ruby.ST.latency_hist::mean 5364.286031
|
||||
system.ruby.ST.latency_hist::gmean 2990.478756
|
||||
system.ruby.ST.latency_hist::stdev 1912.037218
|
||||
system.ruby.ST.latency_hist | 94 10.42% 10.42% | 4 0.44% 10.86% | 3 0.33% 11.20% | 4 0.44% 11.64% | 27 2.99% 14.63% | 441 48.89% 63.53% | 296 32.82% 96.34% | 33 3.66% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 902
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 16
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 159
|
||||
system.ruby.ST.hit_latency_hist::samples 68
|
||||
system.ruby.ST.hit_latency_hist::mean 12.264706
|
||||
system.ruby.ST.hit_latency_hist::gmean 3.346538
|
||||
system.ruby.ST.hit_latency_hist::stdev 31.130739
|
||||
system.ruby.ST.hit_latency_hist | 62 91.18% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 0 0.00% 91.18% | 2 2.94% 94.12% | 4 5.88% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 68
|
||||
system.ruby.ST.hit_latency_hist::samples 73
|
||||
system.ruby.ST.hit_latency_hist::mean 8.506849
|
||||
system.ruby.ST.hit_latency_hist::gmean 2.645743
|
||||
system.ruby.ST.hit_latency_hist::stdev 25.369559
|
||||
system.ruby.ST.hit_latency_hist | 69 94.52% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 0 0.00% 94.52% | 1 1.37% 95.89% | 3 4.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 73
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 1024
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 10239
|
||||
system.ruby.ST.miss_latency_hist::samples 800
|
||||
system.ruby.ST.miss_latency_hist::mean 5832.366250
|
||||
system.ruby.ST.miss_latency_hist::gmean 5611.834584
|
||||
system.ruby.ST.miss_latency_hist::stdev 984.210196
|
||||
system.ruby.ST.miss_latency_hist | 14 1.75% 1.75% | 2 0.25% 2.00% | 2 0.25% 2.25% | 4 0.50% 2.75% | 55 6.88% 9.62% | 446 55.75% 65.38% | 253 31.62% 97.00% | 24 3.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 800
|
||||
system.ruby.ST.miss_latency_hist::samples 829
|
||||
system.ruby.ST.miss_latency_hist::mean 5835.904704
|
||||
system.ruby.ST.miss_latency_hist::gmean 5553.905612
|
||||
system.ruby.ST.miss_latency_hist::stdev 1107.483624
|
||||
system.ruby.ST.miss_latency_hist | 21 2.53% 2.53% | 4 0.48% 3.02% | 3 0.36% 3.38% | 4 0.48% 3.86% | 27 3.26% 7.12% | 441 53.20% 60.31% | 296 35.71% 96.02% | 33 3.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 829
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 256
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 2559
|
||||
system.ruby.IFETCH.latency_hist::samples 57
|
||||
system.ruby.IFETCH.latency_hist::mean 855.263158
|
||||
system.ruby.IFETCH.latency_hist::gmean 754.746405
|
||||
system.ruby.IFETCH.latency_hist::stdev 394.368008
|
||||
system.ruby.IFETCH.latency_hist | 3 5.26% 5.26% | 8 14.04% 19.30% | 15 26.32% 45.61% | 11 19.30% 64.91% | 12 21.05% 85.96% | 6 10.53% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 57
|
||||
system.ruby.IFETCH.latency_hist::samples 46
|
||||
system.ruby.IFETCH.latency_hist::mean 772.847826
|
||||
system.ruby.IFETCH.latency_hist::gmean 703.281758
|
||||
system.ruby.IFETCH.latency_hist::stdev 370.399662
|
||||
system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 10 21.74% 21.74% | 20 43.48% 65.22% | 7 15.22% 80.43% | 3 6.52% 86.96% | 4 8.70% 95.65% | 1 2.17% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 46
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 256
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 2559
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 57
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 855.263158
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 754.746405
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 394.368008
|
||||
system.ruby.IFETCH.miss_latency_hist | 3 5.26% 5.26% | 8 14.04% 19.30% | 15 26.32% 45.61% | 11 19.30% 64.91% | 12 21.05% 85.96% | 6 10.53% 96.49% | 1 1.75% 98.25% | 1 1.75% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 57
|
||||
system.ruby.L1Cache_Controller.Load 43 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 63 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 870 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Inv 559 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 9999 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data_Exclusive 37 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data_all_Acks 857 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.WB_Ack 756 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Load 37 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Ifetch 57 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Store 802 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Inv 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.L1_Replacement 127 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Inv 35 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 6 0.00% 0.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 46
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 772.847826
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 703.281758
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 370.399662
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 10 21.74% 21.74% | 20 43.48% 65.22% | 7 15.22% 80.43% | 3 6.52% 86.96% | 4 8.70% 95.65% | 1 2.17% 97.83% | 0 0.00% 97.83% | 1 2.17% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 46
|
||||
system.ruby.L1Cache_Controller.Load 54 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 54 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 904 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Inv 563 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 10554 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data_Exclusive 50 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Data_all_Acks 875 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.WB_Ack 784 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Load 50 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Ifetch 46 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Store 831 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.NP.Inv 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.L1_Replacement 125 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.Inv 28 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.S.L1_Replacement 10 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.E.Store 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.E.Inv 5 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.E.L1_Replacement 32 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 68 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Inv 73 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 726 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Inv 16 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.L1_Replacement 433 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data_Exclusive 37 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data_all_Acks 41 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.L1_Replacement 8675 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data_all_Acks 800 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 16 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_I.Ifetch 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_I.Inv 429 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_I.WB_Ack 329 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 427 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GET_INSTR 57 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 37 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 802 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 335 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX_old 787 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 283 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement_clean 1213 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Mem_Data 863 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Mem_Ack 857 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.WB_Data 488 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.WB_Data_clean 13 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Ack_all 56 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 837 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 36 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 776 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_PUTX_old 321 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.L1_GETX 5 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 5 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.E.L1_Replacement 44 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Load 4 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Store 72 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Inv 86 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 743 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Inv 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.L1_Replacement 519 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data_Exclusive 50 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Data_all_Acks 38 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.L1_Replacement 9113 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Data_all_Acks 829 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS_I.Data_all_Acks 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_I.Ifetch 8 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_I.Inv 434 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_I.WB_Ack 351 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.SINK_WB_ACK.WB_Ack 433 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GET_INSTR 47 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 50 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 829 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 358 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX_old 826 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 302 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement_clean 1188 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Mem_Data 884 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Mem_Ack 878 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.WB_Data 493 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.WB_Data_clean 27 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Ack_all 43 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 877 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 38 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 49 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 797 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_PUTX_old 309 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.L1_GETX 8 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 38 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GET_INSTR 8 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 1 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 21 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 283 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement_clean 18 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT.L1_PUTX 329 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 507 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 106 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M_I.Mem_Ack 857 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 206 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.WB_Data 488 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 13 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 24 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 302 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement_clean 15 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT.L1_PUTX 351 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 525 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M_I.L1_GET_INSTR 1 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M_I.L1_PUTX_old 124 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M_I.Mem_Ack 878 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.L1_PUTX_old 215 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.WB_Data 493 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.WB_Data_clean 27 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MCT_I.Ack_all 5 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.I_I.Ack_all 51 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 12 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ISS.Mem_Data 36 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 51 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IS.Mem_Data 52 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 231 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IM.Mem_Data 775 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 5 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 6 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 154 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 342 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 832 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Fetch 863 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data 770 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 863 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 770 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.CleanReplacement 87 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Fetch 863 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.Data 770 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.CleanReplacement 87 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 863 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 770 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.I_I.Ack_all 38 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ISS.L2_Replacement_clean 16 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ISS.Mem_Data 49 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IS.L2_Replacement_clean 19 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IS.Mem_Data 38 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IM.L2_Replacement_clean 224 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IM.Mem_Data 797 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 8 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.L1_PUTX 7 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.L1_PUTX_old 178 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.L2_Replacement_clean 351 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 869 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Fetch 884 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Data 795 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 884 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 795 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.CleanReplacement 85 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Fetch 884 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.Data 795 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.CleanReplacement 85 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IM.Memory_Data 884 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Memory_Ack 795 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
@@ -1,391 +1,404 @@
|
||||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
sim_seconds 0.000327 # Number of seconds simulated
|
||||
sim_ticks 327361 # Number of ticks simulated
|
||||
final_tick 327361 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_seconds 0.000338 # Number of seconds simulated
|
||||
sim_ticks 338071 # Number of ticks simulated
|
||||
final_tick 338071 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
||||
sim_freq 1000000000 # Frequency of simulated ticks
|
||||
host_tick_rate 771883 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 124808 # Number of bytes of host memory used
|
||||
host_seconds 0.42 # Real time elapsed on the host
|
||||
host_tick_rate 719839 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 158348 # Number of bytes of host memory used
|
||||
host_seconds 0.47 # Real time elapsed on the host
|
||||
system.voltage_domain.voltage 1 # Voltage in Volts
|
||||
system.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.clk_domain.clock 1 # Clock period in ticks
|
||||
system.ruby.outstanding_req_hist::bucket_size 2
|
||||
system.ruby.outstanding_req_hist::max_bucket 19
|
||||
system.ruby.outstanding_req_hist::samples 1000
|
||||
system.ruby.outstanding_req_hist::mean 15.813000
|
||||
system.ruby.outstanding_req_hist::gmean 15.714362
|
||||
system.ruby.outstanding_req_hist::stdev 1.128408
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.50% | 2 0.20% 0.70% | 2 0.20% 0.90% | 2 0.20% 1.10% | 2 0.20% 1.30% | 69 6.90% 8.20% | 918 91.80% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 1000
|
||||
system.ruby.outstanding_req_hist::samples 987
|
||||
system.ruby.outstanding_req_hist::mean 15.827761
|
||||
system.ruby.outstanding_req_hist::gmean 15.728108
|
||||
system.ruby.outstanding_req_hist::stdev 1.130761
|
||||
system.ruby.outstanding_req_hist | 1 0.10% 0.10% | 2 0.20% 0.30% | 2 0.20% 0.51% | 2 0.20% 0.71% | 2 0.20% 0.91% | 2 0.20% 1.11% | 2 0.20% 1.32% | 52 5.27% 6.59% | 922 93.41% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.outstanding_req_hist::total 987
|
||||
system.ruby.latency_hist::bucket_size 4096
|
||||
system.ruby.latency_hist::max_bucket 40959
|
||||
system.ruby.latency_hist::samples 985
|
||||
system.ruby.latency_hist::mean 5192.155330
|
||||
system.ruby.latency_hist::gmean 1411.192372
|
||||
system.ruby.latency_hist::stdev 6963.102626
|
||||
system.ruby.latency_hist | 695 70.56% 70.56% | 43 4.37% 74.92% | 33 3.35% 78.27% | 91 9.24% 87.51% | 85 8.63% 96.14% | 28 2.84% 98.98% | 9 0.91% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 985
|
||||
system.ruby.latency_hist::samples 972
|
||||
system.ruby.latency_hist::mean 5437.663580
|
||||
system.ruby.latency_hist::gmean 1650.672742
|
||||
system.ruby.latency_hist::stdev 7600.061844
|
||||
system.ruby.latency_hist | 700 72.02% 72.02% | 56 5.76% 77.78% | 10 1.03% 78.81% | 35 3.60% 82.41% | 92 9.47% 91.87% | 63 6.48% 98.35% | 14 1.44% 99.79% | 2 0.21% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.latency_hist::total 972
|
||||
system.ruby.hit_latency_hist::bucket_size 16
|
||||
system.ruby.hit_latency_hist::max_bucket 159
|
||||
system.ruby.hit_latency_hist::samples 78
|
||||
system.ruby.hit_latency_hist::mean 9.089744
|
||||
system.ruby.hit_latency_hist::gmean 2.589753
|
||||
system.ruby.hit_latency_hist::stdev 26.203591
|
||||
system.ruby.hit_latency_hist | 73 93.59% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 0 0.00% 93.59% | 4 5.13% 98.72% | 1 1.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 78
|
||||
system.ruby.hit_latency_hist::samples 57
|
||||
system.ruby.hit_latency_hist::mean 21.684211
|
||||
system.ruby.hit_latency_hist::gmean 4.921220
|
||||
system.ruby.hit_latency_hist::stdev 41.339257
|
||||
system.ruby.hit_latency_hist | 47 82.46% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 0 0.00% 82.46% | 6 10.53% 92.98% | 4 7.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.hit_latency_hist::total 57
|
||||
system.ruby.miss_latency_hist::bucket_size 4096
|
||||
system.ruby.miss_latency_hist::max_bucket 40959
|
||||
system.ruby.miss_latency_hist::samples 907
|
||||
system.ruby.miss_latency_hist::mean 5637.887541
|
||||
system.ruby.miss_latency_hist::gmean 2426.075868
|
||||
system.ruby.miss_latency_hist::stdev 7081.470328
|
||||
system.ruby.miss_latency_hist | 617 68.03% 68.03% | 43 4.74% 72.77% | 33 3.64% 76.41% | 91 10.03% 86.44% | 85 9.37% 95.81% | 28 3.09% 98.90% | 9 0.99% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 907
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 78 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 852 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 930 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 56 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 56 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 8 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 111 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 15 # Number of times a load aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_load 2 # Number of times a load aliased with a pending load
|
||||
system.ruby.network.routers0.percent_links_utilized 1.520569
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 908
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 53
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 903
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1806
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 907
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 7264
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 3816
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65016
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14448
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7256
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 53 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 855 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 908 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 2.898940
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 908
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 855
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 1708
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 53
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1668
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1806
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 1692
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::2 80
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1758
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 7264
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 6840
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 122976
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 3816
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 120096
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14448
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 13536
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 640
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14064
|
||||
system.ruby.miss_latency_hist::samples 915
|
||||
system.ruby.miss_latency_hist::mean 5775.052459
|
||||
system.ruby.miss_latency_hist::gmean 2371.333869
|
||||
system.ruby.miss_latency_hist::stdev 7708.420615
|
||||
system.ruby.miss_latency_hist | 643 70.27% 70.27% | 56 6.12% 76.39% | 10 1.09% 77.49% | 35 3.83% 81.31% | 92 10.05% 91.37% | 63 6.89% 98.25% | 14 1.53% 99.78% | 2 0.22% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.miss_latency_hist::total 915
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_hits 54 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_misses 862 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 916 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_hits 3 # Number of cache demand hits
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_misses 55 # Number of cache demand misses
|
||||
system.ruby.l1_cntrl0.L1Icache.demand_accesses 58 # Number of cache demand accesses
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_load 1 # Number of times a store aliased with a pending load
|
||||
system.ruby.l1_cntrl0.sequencer.store_waiting_on_store 87 # Number of times a store aliased with a pending store
|
||||
system.ruby.l1_cntrl0.sequencer.load_waiting_on_store 3 # Number of times a load aliased with a pending store
|
||||
system.ruby.network.routers0.percent_links_utilized 1.484895
|
||||
system.ruby.network.routers0.msg_count.Request_Control::0 917
|
||||
system.ruby.network.routers0.msg_count.Response_Data::2 860
|
||||
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 55
|
||||
system.ruby.network.routers0.msg_count.Writeback_Data::2 910
|
||||
system.ruby.network.routers0.msg_count.Writeback_Control::0 1823
|
||||
system.ruby.network.routers0.msg_count.Unblock_Control::2 915
|
||||
system.ruby.network.routers0.msg_bytes.Request_Control::0 7336
|
||||
system.ruby.network.routers0.msg_bytes.Response_Data::2 61920
|
||||
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 3960
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 65520
|
||||
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 14584
|
||||
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 7320
|
||||
system.ruby.l2_cntrl0.L2cache.demand_hits 55 # Number of cache demand hits
|
||||
system.ruby.l2_cntrl0.L2cache.demand_misses 862 # Number of cache demand misses
|
||||
system.ruby.l2_cntrl0.L2cache.demand_accesses 917 # Number of cache demand accesses
|
||||
system.ruby.network.routers1.percent_links_utilized 2.834981
|
||||
system.ruby.network.routers1.msg_count.Request_Control::0 917
|
||||
system.ruby.network.routers1.msg_count.Request_Control::1 862
|
||||
system.ruby.network.routers1.msg_count.Response_Data::2 1721
|
||||
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::2 55
|
||||
system.ruby.network.routers1.msg_count.Writeback_Data::2 1689
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::0 1823
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::1 1704
|
||||
system.ruby.network.routers1.msg_count.Writeback_Control::2 73
|
||||
system.ruby.network.routers1.msg_count.Unblock_Control::2 1773
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::0 7336
|
||||
system.ruby.network.routers1.msg_bytes.Request_Control::1 6896
|
||||
system.ruby.network.routers1.msg_bytes.Response_Data::2 123912
|
||||
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::2 3960
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Data::2 121608
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 14584
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 13632
|
||||
system.ruby.network.routers1.msg_bytes.Writeback_Control::2 584
|
||||
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 14184
|
||||
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1619 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 854 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 765 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 2273 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 420 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memReq 1640 # Total number of memory requests
|
||||
system.ruby.dir_cntrl0.memBuffer.memRead 861 # Number of memory reads
|
||||
system.ruby.dir_cntrl0.memBuffer.memWrite 779 # Number of memory writes
|
||||
system.ruby.dir_cntrl0.memBuffer.memRefresh 2346 # Number of memory refreshes
|
||||
system.ruby.dir_cntrl0.memBuffer.memWaitCycles 430 # Delay stalled at the head of the bank queue
|
||||
system.ruby.dir_cntrl0.memBuffer.memInputQ 26 # Delay in the input queue
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 446 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.275479 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 163 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 144 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.totalStalls 456 # Total number of stall cycles
|
||||
system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.278049 # Expected number of stall cycles per request
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankBusy 167 # memory stalls due to busy bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBusBusy 152 # memory stalls due to busy bus
|
||||
system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 21 # memory stalls due to read write turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 60 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 58 # memory stalls due to read read turnaround
|
||||
system.ruby.dir_cntrl0.memBuffer.memArbWait 32 # memory stalls due to arbitration
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 49 3.03% 3.03% | 44 2.72% 5.74% | 48 2.96% 8.71% | 84 5.19% 13.90% | 49 3.03% 16.92% | 52 3.21% 20.14% | 64 3.95% 24.09% | 51 3.15% 27.24% | 40 2.47% 29.71% | 45 2.78% 32.49% | 48 2.96% 35.45% | 41 2.53% 37.99% | 74 4.57% 42.56% | 47 2.90% 45.46% | 51 3.15% 48.61% | 38 2.35% 50.96% | 56 3.46% 54.42% | 62 3.83% 58.25% | 37 2.29% 60.53% | 58 3.58% 64.11% | 46 2.84% 66.95% | 50 3.09% 70.04% | 55 3.40% 73.44% | 36 2.22% 75.66% | 49 3.03% 78.69% | 71 4.39% 83.08% | 52 3.21% 86.29% | 40 2.47% 88.76% | 42 2.59% 91.35% | 33 2.04% 93.39% | 48 2.96% 96.36% | 59 3.64% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1619 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 1.378219
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 854
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 765
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 1690
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::2 80
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 852
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 6832
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 55080
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 13520
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 640
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6816
|
||||
system.ruby.network.routers3.percent_links_utilized 1.932474
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 908
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 854
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 1708
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 53
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1668
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1806
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 1690
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::2 80
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1758
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 7264
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 6832
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 122976
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 3816
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 120096
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14448
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 13520
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::2 640
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14064
|
||||
system.ruby.network.msg_count.Request_Control 5287
|
||||
system.ruby.network.msg_count.Response_Data 5124
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 159
|
||||
system.ruby.network.msg_count.Writeback_Data 5004
|
||||
system.ruby.network.msg_count.Writeback_Control 10730
|
||||
system.ruby.network.msg_count.Unblock_Control 5275
|
||||
system.ruby.network.msg_byte.Request_Control 42296
|
||||
system.ruby.network.msg_byte.Response_Data 368928
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 11448
|
||||
system.ruby.network.msg_byte.Writeback_Data 360288
|
||||
system.ruby.network.msg_byte.Writeback_Control 85840
|
||||
system.ruby.network.msg_byte.Unblock_Control 42200
|
||||
system.ruby.network.routers0.throttle0.link_utilization 1.384710
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 53
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 903
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 3816
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7224
|
||||
system.ruby.network.routers0.throttle1.link_utilization 1.656428
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 908
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 903
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 903
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 907
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7264
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65016
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7224
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7256
|
||||
system.ruby.network.routers1.throttle0.link_utilization 2.959271
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 908
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 903
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 903
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 845
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 906
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7264
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65016
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7224
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6760
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7248
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.838609
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 855
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 53
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 765
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 903
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 847
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 80
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 852
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6840
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 3816
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 55080
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7224
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6776
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 640
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6816
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.453441
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 854
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 765
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 845
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2 80
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 852
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6832
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 55080
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6760
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2 640
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6816
|
||||
system.ruby.network.routers2.throttle1.link_utilization 1.302996
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 845
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6760
|
||||
system.ruby.network.routers3.throttle0.link_utilization 1.384710
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 53
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 903
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 3816
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7224
|
||||
system.ruby.network.routers3.throttle1.link_utilization 2.959271
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 908
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 854
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 903
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 903
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 845
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 906
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7264
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 61488
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65016
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7224
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6760
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7248
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.453441
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 854
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 765
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 845
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2 80
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 852
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6832
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 55080
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6760
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2 640
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6816
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount | 58 3.54% 3.54% | 44 2.68% 6.22% | 40 2.44% 8.66% | 88 5.37% 14.02% | 64 3.90% 17.93% | 67 4.09% 22.01% | 55 3.35% 25.37% | 38 2.32% 27.68% | 52 3.17% 30.85% | 39 2.38% 33.23% | 42 2.56% 35.79% | 42 2.56% 38.35% | 49 2.99% 41.34% | 50 3.05% 44.39% | 48 2.93% 47.32% | 55 3.35% 50.67% | 48 2.93% 53.60% | 48 2.93% 56.52% | 50 3.05% 59.57% | 46 2.80% 62.38% | 49 2.99% 65.37% | 70 4.27% 69.63% | 43 2.62% 72.26% | 63 3.84% 76.10% | 59 3.60% 79.70% | 46 2.80% 82.50% | 53 3.23% 85.73% | 56 3.41% 89.15% | 35 2.13% 91.28% | 46 2.80% 94.09% | 42 2.56% 96.65% | 55 3.35% 100.00% # Number of accesses per bank
|
||||
system.ruby.dir_cntrl0.memBuffer.memBankCount::total 1640 # Number of accesses per bank
|
||||
system.ruby.network.routers2.percent_links_utilized 1.350086
|
||||
system.ruby.network.routers2.msg_count.Request_Control::1 861
|
||||
system.ruby.network.routers2.msg_count.Response_Data::2 861
|
||||
system.ruby.network.routers2.msg_count.Writeback_Data::2 779
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::1 1704
|
||||
system.ruby.network.routers2.msg_count.Writeback_Control::2 73
|
||||
system.ruby.network.routers2.msg_count.Unblock_Control::2 859
|
||||
system.ruby.network.routers2.msg_bytes.Request_Control::1 6888
|
||||
system.ruby.network.routers2.msg_bytes.Response_Data::2 61992
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 56088
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 13632
|
||||
system.ruby.network.routers2.msg_bytes.Writeback_Control::2 584
|
||||
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 6872
|
||||
system.ruby.network.routers3.percent_links_utilized 1.890037
|
||||
system.ruby.network.routers3.msg_count.Request_Control::0 917
|
||||
system.ruby.network.routers3.msg_count.Request_Control::1 862
|
||||
system.ruby.network.routers3.msg_count.Response_Data::2 1721
|
||||
system.ruby.network.routers3.msg_count.ResponseL2hit_Data::2 55
|
||||
system.ruby.network.routers3.msg_count.Writeback_Data::2 1689
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::0 1823
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::1 1704
|
||||
system.ruby.network.routers3.msg_count.Writeback_Control::2 73
|
||||
system.ruby.network.routers3.msg_count.Unblock_Control::2 1774
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::0 7336
|
||||
system.ruby.network.routers3.msg_bytes.Request_Control::1 6896
|
||||
system.ruby.network.routers3.msg_bytes.Response_Data::2 123912
|
||||
system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::2 3960
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Data::2 121608
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 14584
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 13632
|
||||
system.ruby.network.routers3.msg_bytes.Writeback_Control::2 584
|
||||
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 14192
|
||||
system.ruby.network.msg_count.Request_Control 5336
|
||||
system.ruby.network.msg_count.Response_Data 5163
|
||||
system.ruby.network.msg_count.ResponseL2hit_Data 165
|
||||
system.ruby.network.msg_count.Writeback_Data 5067
|
||||
system.ruby.network.msg_count.Writeback_Control 10800
|
||||
system.ruby.network.msg_count.Unblock_Control 5321
|
||||
system.ruby.network.msg_byte.Request_Control 42688
|
||||
system.ruby.network.msg_byte.Response_Data 371736
|
||||
system.ruby.network.msg_byte.ResponseL2hit_Data 11880
|
||||
system.ruby.network.msg_byte.Writeback_Data 364824
|
||||
system.ruby.network.msg_byte.Writeback_Control 86400
|
||||
system.ruby.network.msg_byte.Unblock_Control 42568
|
||||
system.ruby.network.routers0.throttle0.link_utilization 1.352674
|
||||
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 860
|
||||
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 55
|
||||
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 911
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 61920
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 3960
|
||||
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 7288
|
||||
system.ruby.network.routers0.throttle1.link_utilization 1.617116
|
||||
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 917
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 910
|
||||
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 912
|
||||
system.ruby.network.routers0.throttle1.msg_count.Unblock_Control::2 915
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 7336
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 65520
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 7296
|
||||
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 7320
|
||||
system.ruby.network.routers1.throttle0.link_utilization 2.889038
|
||||
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 917
|
||||
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 861
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 910
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::0 912
|
||||
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::1 852
|
||||
system.ruby.network.routers1.throttle0.msg_count.Unblock_Control::2 914
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::0 7336
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Response_Data::2 61992
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 65520
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 7296
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 6816
|
||||
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 7312
|
||||
system.ruby.network.routers1.throttle1.link_utilization 2.780925
|
||||
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 862
|
||||
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 860
|
||||
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 55
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::2 779
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 911
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::1 852
|
||||
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::2 73
|
||||
system.ruby.network.routers1.throttle1.msg_count.Unblock_Control::2 859
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::1 6896
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::2 61920
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::2 3960
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 56088
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7288
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 6816
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::2 584
|
||||
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 6872
|
||||
system.ruby.network.routers2.throttle0.link_utilization 1.428102
|
||||
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 861
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 779
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 852
|
||||
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::2 73
|
||||
system.ruby.network.routers2.throttle0.msg_count.Unblock_Control::2 859
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 6888
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 56088
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 6816
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::2 584
|
||||
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 6872
|
||||
system.ruby.network.routers2.throttle1.link_utilization 1.272070
|
||||
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 861
|
||||
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 852
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 61992
|
||||
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 6816
|
||||
system.ruby.network.routers3.throttle0.link_utilization 1.352674
|
||||
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 860
|
||||
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 55
|
||||
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 911
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 61920
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 3960
|
||||
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 7288
|
||||
system.ruby.network.routers3.throttle1.link_utilization 2.889186
|
||||
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 917
|
||||
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 861
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 910
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::0 912
|
||||
system.ruby.network.routers3.throttle1.msg_count.Writeback_Control::1 852
|
||||
system.ruby.network.routers3.throttle1.msg_count.Unblock_Control::2 915
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::0 7336
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::2 61992
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 65520
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 7296
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 6816
|
||||
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 7320
|
||||
system.ruby.network.routers3.throttle2.link_utilization 1.428250
|
||||
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 862
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 779
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 852
|
||||
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::2 73
|
||||
system.ruby.network.routers3.throttle2.msg_count.Unblock_Control::2 859
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 6896
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 56088
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 6816
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::2 584
|
||||
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 6872
|
||||
system.ruby.LD.latency_hist::bucket_size 4096
|
||||
system.ruby.LD.latency_hist::max_bucket 40959
|
||||
system.ruby.LD.latency_hist::samples 44
|
||||
system.ruby.LD.latency_hist::mean 5510.704545
|
||||
system.ruby.LD.latency_hist::gmean 869.978187
|
||||
system.ruby.LD.latency_hist::stdev 7880.576607
|
||||
system.ruby.LD.latency_hist | 32 72.73% 72.73% | 0 0.00% 72.73% | 1 2.27% 75.00% | 4 9.09% 84.09% | 5 11.36% 95.45% | 1 2.27% 97.73% | 1 2.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 44
|
||||
system.ruby.LD.latency_hist::samples 43
|
||||
system.ruby.LD.latency_hist::mean 6256.744186
|
||||
system.ruby.LD.latency_hist::gmean 1688.376032
|
||||
system.ruby.LD.latency_hist::stdev 8068.365932
|
||||
system.ruby.LD.latency_hist | 29 67.44% 67.44% | 1 2.33% 69.77% | 1 2.33% 72.09% | 3 6.98% 79.07% | 4 9.30% 88.37% | 5 11.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.latency_hist::total 43
|
||||
system.ruby.LD.hit_latency_hist::bucket_size 1
|
||||
system.ruby.LD.hit_latency_hist::max_bucket 9
|
||||
system.ruby.LD.hit_latency_hist::samples 6
|
||||
system.ruby.LD.hit_latency_hist::mean 2.166667
|
||||
system.ruby.LD.hit_latency_hist::gmean 1.906369
|
||||
system.ruby.LD.hit_latency_hist::stdev 1.169045
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 2 33.33% 33.33% | 2 33.33% 66.67% | 1 16.67% 83.33% | 1 16.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 6
|
||||
system.ruby.LD.hit_latency_hist::samples 3
|
||||
system.ruby.LD.hit_latency_hist::mean 3.666667
|
||||
system.ruby.LD.hit_latency_hist::gmean 3.634241
|
||||
system.ruby.LD.hit_latency_hist::stdev 0.577350
|
||||
system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 33.33% 33.33% | 2 66.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.hit_latency_hist::total 3
|
||||
system.ruby.LD.miss_latency_hist::bucket_size 4096
|
||||
system.ruby.LD.miss_latency_hist::max_bucket 40959
|
||||
system.ruby.LD.miss_latency_hist::samples 38
|
||||
system.ruby.LD.miss_latency_hist::mean 6380.473684
|
||||
system.ruby.LD.miss_latency_hist::gmean 2287.694735
|
||||
system.ruby.LD.miss_latency_hist::stdev 8153.326443
|
||||
system.ruby.LD.miss_latency_hist | 26 68.42% 68.42% | 0 0.00% 68.42% | 1 2.63% 71.05% | 4 10.53% 81.58% | 5 13.16% 94.74% | 1 2.63% 97.37% | 1 2.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 38
|
||||
system.ruby.LD.miss_latency_hist::samples 40
|
||||
system.ruby.LD.miss_latency_hist::mean 6725.725000
|
||||
system.ruby.LD.miss_latency_hist::gmean 2676.075339
|
||||
system.ruby.LD.miss_latency_hist::stdev 8177.576523
|
||||
system.ruby.LD.miss_latency_hist | 26 65.00% 65.00% | 1 2.50% 67.50% | 1 2.50% 70.00% | 3 7.50% 77.50% | 4 10.00% 87.50% | 5 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.LD.miss_latency_hist::total 40
|
||||
system.ruby.ST.latency_hist::bucket_size 4096
|
||||
system.ruby.ST.latency_hist::max_bucket 40959
|
||||
system.ruby.ST.latency_hist::samples 885
|
||||
system.ruby.ST.latency_hist::mean 5462.276836
|
||||
system.ruby.ST.latency_hist::gmean 1523.559741
|
||||
system.ruby.ST.latency_hist::stdev 7040.777523
|
||||
system.ruby.ST.latency_hist | 607 68.59% 68.59% | 43 4.86% 73.45% | 32 3.62% 77.06% | 87 9.83% 86.89% | 80 9.04% 95.93% | 27 3.05% 98.98% | 8 0.90% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 885
|
||||
system.ruby.ST.latency_hist::samples 872
|
||||
system.ruby.ST.latency_hist::mean 5714.713303
|
||||
system.ruby.ST.latency_hist::gmean 1797.126289
|
||||
system.ruby.ST.latency_hist::stdev 7719.803155
|
||||
system.ruby.ST.latency_hist | 614 70.41% 70.41% | 55 6.31% 76.72% | 9 1.03% 77.75% | 32 3.67% 81.42% | 88 10.09% 91.51% | 58 6.65% 98.17% | 14 1.61% 99.77% | 2 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.latency_hist::total 872
|
||||
system.ruby.ST.hit_latency_hist::bucket_size 16
|
||||
system.ruby.ST.hit_latency_hist::max_bucket 159
|
||||
system.ruby.ST.hit_latency_hist::samples 72
|
||||
system.ruby.ST.hit_latency_hist::mean 9.666667
|
||||
system.ruby.ST.hit_latency_hist::gmean 2.656722
|
||||
system.ruby.ST.hit_latency_hist::stdev 27.206047
|
||||
system.ruby.ST.hit_latency_hist | 67 93.06% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 0 0.00% 93.06% | 4 5.56% 98.61% | 1 1.39% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 72
|
||||
system.ruby.ST.hit_latency_hist::samples 51
|
||||
system.ruby.ST.hit_latency_hist::mean 21.803922
|
||||
system.ruby.ST.hit_latency_hist::gmean 4.911597
|
||||
system.ruby.ST.hit_latency_hist::stdev 41.550942
|
||||
system.ruby.ST.hit_latency_hist | 42 82.35% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 0 0.00% 82.35% | 5 9.80% 92.16% | 4 7.84% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.hit_latency_hist::total 51
|
||||
system.ruby.ST.miss_latency_hist::bucket_size 4096
|
||||
system.ruby.ST.miss_latency_hist::max_bucket 40959
|
||||
system.ruby.ST.miss_latency_hist::samples 813
|
||||
system.ruby.ST.miss_latency_hist::mean 5945.164822
|
||||
system.ruby.ST.miss_latency_hist::gmean 2673.966009
|
||||
system.ruby.ST.miss_latency_hist::stdev 7148.312268
|
||||
system.ruby.ST.miss_latency_hist | 535 65.81% 65.81% | 43 5.29% 71.09% | 32 3.94% 75.03% | 87 10.70% 85.73% | 80 9.84% 95.57% | 27 3.32% 98.89% | 8 0.98% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 813
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 256
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 2559
|
||||
system.ruby.IFETCH.latency_hist::samples 56
|
||||
system.ruby.IFETCH.latency_hist::mean 672.982143
|
||||
system.ruby.IFETCH.latency_hist::gmean 614.909107
|
||||
system.ruby.IFETCH.latency_hist::stdev 260.614623
|
||||
system.ruby.IFETCH.latency_hist | 4 7.14% 7.14% | 9 16.07% 23.21% | 24 42.86% 66.07% | 17 30.36% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 56
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 256
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 2559
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 56
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 672.982143
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 614.909107
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 260.614623
|
||||
system.ruby.IFETCH.miss_latency_hist | 4 7.14% 7.14% | 9 16.07% 23.21% | 24 42.86% 66.07% | 17 30.36% 96.43% | 1 1.79% 98.21% | 1 1.79% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 56
|
||||
system.ruby.ST.miss_latency_hist::samples 821
|
||||
system.ruby.ST.miss_latency_hist::mean 6068.353228
|
||||
system.ruby.ST.miss_latency_hist::gmean 2593.060445
|
||||
system.ruby.ST.miss_latency_hist::stdev 7820.542647
|
||||
system.ruby.ST.miss_latency_hist | 563 68.57% 68.57% | 55 6.70% 75.27% | 9 1.10% 76.37% | 32 3.90% 80.27% | 88 10.72% 90.99% | 58 7.06% 98.05% | 14 1.71% 99.76% | 2 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.ST.miss_latency_hist::total 821
|
||||
system.ruby.IFETCH.latency_hist::bucket_size 128
|
||||
system.ruby.IFETCH.latency_hist::max_bucket 1279
|
||||
system.ruby.IFETCH.latency_hist::samples 57
|
||||
system.ruby.IFETCH.latency_hist::mean 581.385965
|
||||
system.ruby.IFETCH.latency_hist::gmean 442.065920
|
||||
system.ruby.IFETCH.latency_hist::stdev 271.884544
|
||||
system.ruby.IFETCH.latency_hist | 3 5.26% 5.26% | 3 5.26% 10.53% | 9 15.79% 26.32% | 6 10.53% 36.84% | 11 19.30% 56.14% | 10 17.54% 73.68% | 8 14.04% 87.72% | 3 5.26% 92.98% | 4 7.02% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.latency_hist::total 57
|
||||
system.ruby.IFETCH.hit_latency_hist::bucket_size 16
|
||||
system.ruby.IFETCH.hit_latency_hist::max_bucket 159
|
||||
system.ruby.IFETCH.hit_latency_hist::samples 3
|
||||
system.ruby.IFETCH.hit_latency_hist::mean 37.666667
|
||||
system.ruby.IFETCH.hit_latency_hist::gmean 6.889419
|
||||
system.ruby.IFETCH.hit_latency_hist::stdev 61.784572
|
||||
system.ruby.IFETCH.hit_latency_hist | 2 66.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 1 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.hit_latency_hist::total 3
|
||||
system.ruby.IFETCH.miss_latency_hist::bucket_size 128
|
||||
system.ruby.IFETCH.miss_latency_hist::max_bucket 1279
|
||||
system.ruby.IFETCH.miss_latency_hist::samples 54
|
||||
system.ruby.IFETCH.miss_latency_hist::mean 611.592593
|
||||
system.ruby.IFETCH.miss_latency_hist::gmean 557.048280
|
||||
system.ruby.IFETCH.miss_latency_hist::stdev 245.556320
|
||||
system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 3 5.56% 5.56% | 9 16.67% 22.22% | 6 11.11% 33.33% | 11 20.37% 53.70% | 10 18.52% 72.22% | 8 14.81% 87.04% | 3 5.56% 92.59% | 4 7.41% 100.00% | 0 0.00% 100.00%
|
||||
system.ruby.IFETCH.miss_latency_hist::total 54
|
||||
system.ruby.L1Cache_Controller.Load 44 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 192 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 1001 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 465203 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 907 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 903 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 813 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 905 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 38 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 56 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 814 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Ifetch 307 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Store 1014 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.L1_Replacement 481138 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Exclusive_Data 915 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Writeback_Ack_Data 911 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.All_acks 821 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.Use_Timeout 914 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Load 40 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Ifetch 55 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.I.Store 822 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.Ifetch 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M.L1_Replacement 92 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 1319 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Ifetch 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.L1_Replacement 1461 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.M_W.Use_Timeout 93 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 66 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 811 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 6 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 29843 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 812 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.L1_Replacement 399867 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 813 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.L1_Replacement 17168 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 813 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.L1_Replacement 16103 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Load 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.Store 49 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM.L1_Replacement 820 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Load 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Store 2 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.L1_Replacement 30008 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MM_W.Use_Timeout 821 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.L1_Replacement 410291 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IM.Exclusive_Data 821 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.L1_Replacement 20607 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.OM.All_acks 821 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.L1_Replacement 17859 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.IS.Exclusive_Data 94 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Ifetch 136 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Store 115 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 903 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 127 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 895 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 2308 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 766 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 766 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data_Exclusive 88 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 86 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 817 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 845 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 906 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 847 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 88 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 767 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 903 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 6 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 47 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 847 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_GETS 33 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 86 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 817 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.L1_PUTX 65 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data_Exclusive 88 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 87 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 766 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.L1_PUTX 1324 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 766 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 766 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.L1_PUTX 5 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 47 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.L1_PUTX 11 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 6 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.L1_GETX 81 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 845 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 837 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 88 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 845 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 852 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Clean_Writeback 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 765 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 854 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 765 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 766 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 88 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 760 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 845 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Exclusive_Unblock 87 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 88 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Ack 1 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 765 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 766 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Ack 4 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.GETX 71 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Clean_Writeback 80 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 765 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Load 1 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Ifetch 249 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Store 141 0.00% 0.00%
|
||||
system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 911 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETS 142 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_GETX 948 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_PUTX 2296 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.All_Acks 782 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data 782 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Data_Exclusive 79 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBCLEANDATA 77 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 833 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Writeback_Ack 852 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.Exclusive_Unblock 914 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.L2_Replacement 923 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETS 80 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.NP.L1_GETX 782 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILX.L1_PUTX 912 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETS 15 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L1_GETX 40 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.M.L2_Replacement 852 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_GETS 30 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_GETX 85 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBCLEANDATA 77 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 833 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.L1_PUTX 25 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Data_Exclusive 79 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGS.Exclusive_Unblock 78 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGM.Data 782 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.L1_PUTX 1344 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.All_Acks 782 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 781 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.L1_PUTX 15 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 40 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 15 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.OO.L2_Replacement 71 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.L1_GETS 17 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.L1_GETX 41 0.00% 0.00%
|
||||
system.ruby.L2Cache_Controller.MI.Writeback_Ack 852 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETX 792 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.GETS 79 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.PUTX 852 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Exclusive_Unblock 859 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Clean_Writeback 73 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Dirty_Writeback 779 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Data 861 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.Memory_Ack 779 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETX 782 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.GETS 79 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.I.Memory_Ack 775 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.M.PUTX 852 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Exclusive_Unblock 78 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Data 79 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.IS.Memory_Ack 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Exclusive_Unblock 781 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Data 782 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MM.Memory_Ack 2 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.GETX 10 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Clean_Writeback 73 0.00% 0.00%
|
||||
system.ruby.Directory_Controller.MI.Dirty_Writeback 779 0.00% 0.00%
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user