misc: Stop excluding code when building the NULL ISA.

The BaseCPU needs a little extra hacking because it tries to create
default objects based on what the ISA is. If the ISA isn't recognized,
then the types will be set to None, and some extra checks have been
added as the type is set up.

Change-Id: Ia3cae313e1a96a953d2316d9192f41a8fd28c141
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62195
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-25 05:44:13 -07:00
parent aefc0576a2
commit a13e3debed
19 changed files with 16 additions and 81 deletions

View File

@@ -47,9 +47,6 @@ DebugFlag('DMA')
SimObject('Platform.py', sim_objects=['Platform'])
Source('platform.cc')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('BadDevice.py', sim_objects=['BadDevice'])
Source('baddev.cc')

View File

@@ -37,8 +37,5 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('I2C.py', sim_objects=['I2CDevice', 'I2CBus'])
Source('bus.cc')

View File

@@ -868,12 +868,10 @@ DistIface::toggleSync(ThreadContext *tc)
// stop point. Suspend execution of all local thread contexts.
// Dist-gem5 will reactivate all thread contexts when everyone has
// reached the sync stop point.
#if !IS_NULL_ISA
for (auto *tc: primary->sys->threads) {
if (tc->status() == ThreadContext::Active)
tc->quiesce();
}
#endif
} else {
inform("Request toggling syncronization on\n");
primary->syncEvent->start();
@@ -882,12 +880,10 @@ DistIface::toggleSync(ThreadContext *tc)
// nodes to prevent causality errors. We can also schedule CPU
// activation here, since we know exactly when the next sync will
// occur.
#if !IS_NULL_ISA
for (auto *tc: primary->sys->threads) {
if (tc->status() == ThreadContext::Active)
tc->quiesceTick(primary->syncEvent->when() + 1);
}
#endif
}
}

View File

@@ -37,9 +37,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('PS2.py', sim_objects=[
'PS2Device', 'PS2Keyboard', 'PS2Mouse', 'PS2TouchKit'])
Source('device.cc')

View File

@@ -40,9 +40,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('Serial.py', sim_objects=['SerialDevice', 'SerialNullDevice'])
SimObject('Terminal.py', sim_objects=['Terminal'], enums=['TerminalDump'])
SimObject('Uart.py', sim_objects=['Uart', 'SimpleUart', 'Uart8250'])

View File

@@ -40,9 +40,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
# Controllers
SimObject('Ide.py', sim_objects=['IdeDisk', 'IdeController'], enums=['IdeID'])

View File

@@ -37,9 +37,6 @@
Import('*')
if env['CONF']['TARGET_ISA'] == 'null':
Return()
SimObject('VirtIO.py', sim_objects=[
'VirtIODeviceBase', 'VirtIODummyDevice', 'PciVirtIO'])
SimObject('VirtIOConsole.py', sim_objects=['VirtIOConsole'])