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ARM: Implemented prefetch instructions/decoding (pli, pld, pldw).

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This commit is contained in:
Gabe Black
2010-06-02 12:58:05 -05:00
parent 61b00d3224
commit a1253ec644
2 changed files with 121 additions and 11 deletions
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92
src/arch/arm/isa/formats/uncond.isa
View File

@@ -60,11 +60,38 @@ def format ArmUnconditional() {{
// Unallocated memory hint
return new WarnUnimplemented("nop", machInst);
} else if (bits(op1, 2, 0) == 5) {
return new WarnUnimplemented("pli", machInst);
const bool add = bits(machInst, 23);
const uint32_t imm12 = bits(machInst, 11, 0);
if (add) {
return new %(pli_iadd)s(machInst, INTREG_ZERO,
rn, add, imm12);
} else {
return new %(pli_isub)s(machInst, INTREG_ZERO,
rn, add, imm12);
}
}
} else if (bits(op1, 6, 4) == 0x5) {
if (bits(op1, 1, 0) == 0x1) {
return new WarnUnimplemented("pld", machInst);
const bool add = bits(machInst, 23);
const bool pldw = bits(machInst, 22);
const uint32_t imm12 = bits(machInst, 11, 0);
if (pldw) {
if (add) {
return new %(pldw_iadd)s(machInst, INTREG_ZERO,
rn, add, imm12);
} else {
return new %(pldw_isub)s(machInst, INTREG_ZERO,
rn, add, imm12);
}
} else {
if (add) {
return new %(pld_iadd)s(machInst, INTREG_ZERO,
rn, add, imm12);
} else {
return new %(pld_isub)s(machInst, INTREG_ZERO,
rn, add, imm12);
}
}
} else if (op1 == 0x57) {
switch (op2) {
case 0x1:
@@ -83,9 +110,51 @@ def format ArmUnconditional() {{
// Unallocated memory hint
return new WarnUnimplemented("nop", machInst);
case 0x65:
return new WarnUnimplemented("pli", machInst);
{
const uint32_t imm5 = bits(machInst, 11, 7);
const uint32_t type = bits(machInst, 6, 5);
const bool add = bits(machInst, 23);
const IntRegIndex rm =
(IntRegIndex)(uint32_t)bits(machInst, 3, 0);
if (add) {
return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
add, imm5, type, rm);
} else {
return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
add, imm5, type, rm);
}
}
case 0x71:
return new WarnUnimplemented("pld", machInst);
case 0x75:
{
const uint32_t imm5 = bits(machInst, 11, 7);
const uint32_t type = bits(machInst, 6, 5);
const bool add = bits(machInst, 23);
const bool pldw = bits(machInst, 22);
const IntRegIndex rm =
(IntRegIndex)(uint32_t)bits(machInst, 3, 0);
if (pldw) {
if (add) {
return new %(pldw_radd)s(machInst, INTREG_ZERO,
rn, add, imm5,
type, rm);
} else {
return new %(pldw_rsub)s(machInst, INTREG_ZERO,
rn, add, imm5,
type, rm);
}
} else {
if (add) {
return new %(pld_radd)s(machInst, INTREG_ZERO,
rn, add, imm5,
type, rm);
} else {
return new %(pld_rsub)s(machInst, INTREG_ZERO,
rn, add, imm5,
type, rm);
}
}
}
}
}
} else {
@@ -151,5 +220,18 @@ def format ArmUnconditional() {{
}
return new Unknown(machInst);
}
'''
''' % {
"pli_iadd" : "PLI_" + loadImmClassName(False, True, False, 1),
"pli_isub" : "PLI_" + loadImmClassName(False, False, False, 1),
"pld_iadd" : "PLD_" + loadImmClassName(False, True, False, 1),
"pld_isub" : "PLD_" + loadImmClassName(False, False, False, 1),
"pldw_iadd" : "PLDW_" + loadImmClassName(False, True, False, 1),
"pldw_isub" : "PLDW_" + loadImmClassName(False, False, False, 1),
"pli_radd" : "PLI_" + loadRegClassName(False, True, False, 1),
"pli_rsub" : "PLI_" + loadRegClassName(False, False, False, 1),
"pld_radd" : "PLD_" + loadRegClassName(False, True, False, 1),
"pld_rsub" : "PLD_" + loadRegClassName(False, False, False, 1),
"pldw_radd" : "PLDW_" + loadRegClassName(False, True, False, 1),
"pldw_rsub" : "PLDW_" + loadRegClassName(False, False, False, 1)
};
}};

40
src/arch/arm/isa/insts/ldr.isa
View File

@@ -74,7 +74,7 @@ let {{
exec_output += newExec
def buildImmLoad(mnem, post, add, writeback, \
size=4, sign=False, user=False):
size=4, sign=False, user=False, prefetch=False):
name = mnem
Name = loadImmClassName(post, add, writeback, \
size, sign, user)
@@ -90,15 +90,24 @@ let {{
eaCode += offset
eaCode += ";"
accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
if prefetch:
Name = "%s_%s" % (mnem.upper(), Name)
memFlags = ["Request::PREFETCH"]
accCode = '''
uint64_t temp = Mem%s;\n
temp = temp;
''' % buildMemSuffix(sign, size)
else:
memFlags = []
accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryImm", post, writeback)
emitLoad(name, Name, True, eaCode, accCode, [], [], base)
emitLoad(name, Name, True, eaCode, accCode, memFlags, [], base)
def buildRegLoad(mnem, post, add, writeback, \
size=4, sign=False, user=False):
size=4, sign=False, user=False, prefetch=False):
name = mnem
Name = loadRegClassName(post, add, writeback,
size, sign, user)
@@ -115,12 +124,21 @@ let {{
eaCode += offset
eaCode += ";"
accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
if prefetch:
Name = "%s_%s" % (mnem.upper(), Name)
memFlags = ["Request::PREFETCH"]
accCode = '''
uint64_t temp = Mem%s;\n
temp = temp;
''' % buildMemSuffix(sign, size)
else:
memFlags = []
accCode = "IWDest = Mem%s;\n" % buildMemSuffix(sign, size)
if writeback:
accCode += "Base = Base %s;\n" % offset
base = buildMemBase("MemoryReg", post, writeback)
emitLoad(name, Name, False, eaCode, accCode, [], [], base)
emitLoad(name, Name, False, eaCode, accCode, memFlags, [], base)
def buildDoubleImmLoad(mnem, post, add, writeback):
name = mnem
@@ -201,6 +219,12 @@ let {{
buildDoubleImmLoad(mnem, False, False, False)
buildDoubleRegLoad(mnem, False, False, False)
def buildPrefetches(mnem):
buildRegLoad(mnem, False, False, False, size=1, prefetch=True)
buildImmLoad(mnem, False, False, False, size=1, prefetch=True)
buildRegLoad(mnem, False, True, False, size=1, prefetch=True)
buildImmLoad(mnem, False, True, False, size=1, prefetch=True)
buildLoads("ldr")
buildLoads("ldrt", user=True)
buildLoads("ldrb", size=1)
@@ -213,4 +237,8 @@ let {{
buildLoads("ldrsht", size=2, sign=True, user=True)
buildDoubleLoads("ldrd")
buildPrefetches("pld")
buildPrefetches("pldw")
buildPrefetches("pli")
}};