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cpu, arch: Replace the CCReg type with RegVal.

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Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2018-11-21 16:20:57 -08:00
parent fbdf0b689e
commit a119a96324
23 changed files with 56 additions and 77 deletions
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8
src/cpu/thread_context.cc
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@@ -108,8 +108,8 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
// loop through the Condition Code registers.
for (int i = 0; i < TheISA::NumCCRegs; ++i) {
TheISA::CCReg t1 = one->readCCReg(i);
TheISA::CCReg t2 = two->readCCReg(i);
RegVal t1 = one->readCCReg(i);
RegVal t2 = two->readCCReg(i);
if (t1 != t2)
panic("CC reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
@@ -192,7 +192,7 @@ serialize(ThreadContext &tc, CheckpointOut &cp)
SERIALIZE_ARRAY(intRegs, NumIntRegs);
#ifdef ISA_HAS_CC_REGS
CCReg ccRegs[NumCCRegs];
RegVal ccRegs[NumCCRegs];
for (int i = 0; i < NumCCRegs; ++i)
ccRegs[i] = tc.readCCRegFlat(i);
SERIALIZE_ARRAY(ccRegs, NumCCRegs);
@@ -233,7 +233,7 @@ unserialize(ThreadContext &tc, CheckpointIn &cp)
tc.setIntRegFlat(i, intRegs[i]);
#ifdef ISA_HAS_CC_REGS
CCReg ccRegs[NumCCRegs];
RegVal ccRegs[NumCCRegs];
UNSERIALIZE_ARRAY(ccRegs, NumCCRegs);
for (int i = 0; i < NumCCRegs; ++i)
tc.setCCRegFlat(i, ccRegs[i]);