cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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@@ -100,7 +100,6 @@ class SimpleThread : public ThreadState
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{
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protected:
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typedef TheISA::MachInst MachInst;
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typedef TheISA::CCReg CCReg;
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using VecRegContainer = TheISA::VecRegContainer;
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using VecElem = TheISA::VecElem;
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using VecPredRegContainer = TheISA::VecPredRegContainer;
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@@ -113,7 +112,7 @@ class SimpleThread : public ThreadState
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VecRegContainer vecRegs[TheISA::NumVecRegs];
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VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
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#ifdef ISA_HAS_CC_REGS
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TheISA::CCReg ccRegs[TheISA::NumCCRegs];
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RegVal ccRegs[TheISA::NumCCRegs];
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#endif
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TheISA::ISA *const isa; // one "instance" of the current ISA.
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@@ -379,7 +378,8 @@ class SimpleThread : public ThreadState
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return regVal;
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}
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CCReg readCCReg(int reg_idx)
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RegVal
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readCCReg(int reg_idx)
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{
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#ifdef ISA_HAS_CC_REGS
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int flatIndex = isa->flattenCCIndex(reg_idx);
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@@ -449,7 +449,7 @@ class SimpleThread : public ThreadState
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}
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void
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setCCReg(int reg_idx, CCReg val)
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setCCReg(int reg_idx, RegVal val)
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{
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#ifdef ISA_HAS_CC_REGS
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int flatIndex = isa->flattenCCIndex(reg_idx);
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@@ -622,13 +622,13 @@ class SimpleThread : public ThreadState
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}
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#ifdef ISA_HAS_CC_REGS
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CCReg readCCRegFlat(int idx) { return ccRegs[idx]; }
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void setCCRegFlat(int idx, CCReg val) { ccRegs[idx] = val; }
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RegVal readCCRegFlat(int idx) { return ccRegs[idx]; }
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void setCCRegFlat(int idx, RegVal val) { ccRegs[idx] = val; }
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#else
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CCReg readCCRegFlat(int idx)
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RegVal readCCRegFlat(int idx)
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{ panic("readCCRegFlat w/no CC regs!\n"); }
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void setCCRegFlat(int idx, CCReg val)
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void setCCRegFlat(int idx, RegVal val)
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{ panic("setCCRegFlat w/no CC regs!\n"); }
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#endif
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};
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