cpu, arch: Replace the CCReg type with RegVal.

Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.

Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/alpha/registers.hh

@@ -46,9 +46,6 @@ using AlphaISAInst::MaxInstDestRegs;
 // Locked read/write flags are can't be detected by the ISA parser
 const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to Alpha
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/arm/registers.hh

@@ -77,9 +77,6 @@ using VecPredRegContainer = ::DummyVecPredRegContainer;
 constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
 constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 
-// condition code register; must be at least 32 bits for FpCondCodes
-typedef uint64_t CCReg;
-
 // Constants Related to the number of registers
 const int NumIntArchRegs = NUM_ARCH_INTREGS;
 // The number of single precision floating point registers

src/arch/mips/registers.hh

@@ -283,9 +283,6 @@ const int NumMiscRegs = MISCREG_NUMREGS;
 
 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to MIPS
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/null/registers.hh

@@ -47,7 +47,6 @@
 
 namespace NullISA {
 
-typedef uint8_t CCReg;
 const RegIndex ZeroReg = 0;
 
 // Not applicable to null

src/arch/power/registers.hh

@@ -46,9 +46,6 @@ using PowerISAInst::MaxInstDestRegs;
 // be detected by it. Manually add it here.
 const int MaxMiscDestRegs = PowerISAInst::MaxMiscDestRegs + 1;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to Power
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/riscv/registers.hh

@@ -64,8 +64,6 @@ using RiscvISAInst::MaxInstSrcRegs;
 using RiscvISAInst::MaxInstDestRegs;
 const int MaxMiscDestRegs = 1;
 
-typedef uint8_t CCReg; // Not applicable to Riscv
-
 // Not applicable to RISC-V
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/sparc/registers.hh

@@ -46,9 +46,6 @@ using SparcISAInst::MaxInstSrcRegs;
 using SparcISAInst::MaxInstDestRegs;
 using SparcISAInst::MaxMiscDestRegs;
 
-// dummy typedef since we don't have CC regs
-typedef uint8_t CCReg;
-
 // Not applicable to SPARC
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/x86/registers.hh

@@ -96,8 +96,6 @@ const int FramePointerReg = INTREG_RBP;
 // value
 const int SyscallPseudoReturnReg = INTREG_RDX;
 
-typedef uint64_t CCReg;
-
 // Not applicable to x86
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;