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arch-arm: Modify the AAPCS32 ABI implementation to use VecElems.

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Use the VecElem register file when using the 32 bit ARM ABI. This is not
only consistent with an upcoming change which will make the 64 bit
vector registers and the 32 bit vector elements no longer act as views
into the same data, it also simplifies the implementation a little.

Change-Id: Ie8f17b764402a6331012f13b7605520512c2d5c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50207
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-09-09 19:44:55 -07:00
parent 4d398302c4
commit a024c9f19e
1 changed files with 19 additions and 12 deletions
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31
src/arch/arm/aapcs32.hh
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@@ -475,10 +475,14 @@ struct Result<Aapcs32Vfp, Float, typename std::enable_if_t<
return;
}
RegId id(VecRegClass, 0);
auto reg = tc->readVecReg(id);
reg.as<Float>()[0] = f;
tc->setVecReg(id, reg);
auto bytes = floatToBits(f);
auto *vec_elems = static_cast<ArmISA::VecElem *>(&bytes);
constexpr int chunks = sizeof(Float) / sizeof(ArmISA::VecElem);
for (int chunk = 0; chunk < chunks; chunk++) {
int reg = chunk / ArmISA::NumVecElemPerVecReg;
int elem = chunk % ArmISA::NumVecElemPerVecReg;
tc->setVecElem(RegId(VecElemClass, reg, elem), vec_elems[chunk]);
}
};
};
@@ -494,17 +498,20 @@ struct Argument<Aapcs32Vfp, Float, typename std::enable_if_t<
const int index = state.allocate(Float{}, 1);
if (index >= 0) {
constexpr int lane_per_reg = 16 / sizeof(Float);
const int reg = index / lane_per_reg;
const int lane = index % lane_per_reg;
if (index < 0)
return loadFromStack<Float>(tc, state);
RegId id(VecRegClass, reg);
auto val = tc->readVecReg(id);
return val.as<Float>()[lane];
decltype(floatToBits(Float{})) result;
auto *vec_elems = static_cast<ArmISA::VecElem *>(&result);
constexpr int chunks = sizeof(Float) / sizeof(ArmISA::VecElem);
for (int chunk = 0; chunk < chunks; chunk++) {
int reg = chunk / ArmISA::NumVecElemPerVecReg;
int elem = chunk % ArmISA::NumVecElemPerVecReg;
vec_elems[chunk] = tc->readVecElem(RegId(VecElemClass, reg, elem));
}
return loadFromStack<Float>(tc, state);
return bitsToFloat(result);
}
};