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X86: Implement shift-by-one instructions, and make register shifts use registers.

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--HG--
extra : convert_revision : ce4af3e56b45821e0a8b27f288b532d2f9dd3336
This commit is contained in:
Gabe Black
2007-07-26 22:09:24 -07:00
parent c0670187c5
commit 9e975a7e08
1 changed files with 69 additions and 23 deletions
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92
src/arch/x86/isa/insts/rotate_and_shift/shift.py
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@@ -74,15 +74,35 @@ def macroop SAL_P_I
st t1, ds, [0, t0, t7], disp
};
def macroop SAL_1_R
{
slli reg, reg, 1
};
def macroop SAL_1_M
{
ld t1, ds, [scale, index, base], disp
slli t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop SAL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
slli t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop SAL_R_R
{
slli reg, reg, regm
sll reg, reg, regm
};
def macroop SAL_M_R
{
ld t1, ds, [scale, index, base], disp
slli t1, t1, reg
sll t1, t1, reg
st t1, ds, [scale, index, base], disp
};
@@ -90,7 +110,7 @@ def macroop SAL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
slli t1, t1, reg
sll t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
@@ -114,15 +134,35 @@ def macroop SHR_P_I
st t1, ds, [0, t0, t7], disp
};
def macroop SHR_1_R
{
srli reg, reg, 1
};
def macroop SHR_1_M
{
ld t1, ds, [scale, index, base], disp
srli t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop SHR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srli t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop SHR_R_R
{
srli reg, reg, regm
srl reg, reg, regm
};
def macroop SHR_M_R
{
ld t1, ds, [scale, index, base], disp
srli t1, t1, reg
srl t1, t1, reg
st t1, ds, [scale, index, base], disp
};
@@ -130,7 +170,7 @@ def macroop SHR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srli t1, t1, reg
srl t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
@@ -154,15 +194,35 @@ def macroop SAR_P_I
st t1, ds, [0, t0, t7], disp
};
def macroop SAR_1_R
{
srai reg, reg, 1
};
def macroop SAR_1_M
{
ld t1, ds, [scale, index, base], disp
srai t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop SAR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srai t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop SAR_R_R
{
srai reg, reg, regm
sra reg, reg, regm
};
def macroop SAR_M_R
{
ld t1, ds, [scale, index, base], disp
srai t1, t1, reg
sra t1, t1, reg
st t1, ds, [scale, index, base], disp
};
@@ -170,21 +230,7 @@ def macroop SAR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srai t1, t1, reg
sra t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class SAL(Inst):
# "GenFault ${new UnimpInstFault}"
# class SAR(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHL(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHR(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHLD(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHRD(Inst):
# "GenFault ${new UnimpInstFault}"
#}};