ruby: change slicc to allow for constructor args

The patch adds support to slicc for recognizing arguments that should be
passed to the constructor of a class. I did not like the fact that an explicit
check was being carried on the type 'TBETable' to figure out the arguments to
be passed to the constructor.
The patch also moves some of the member variables that are declared for all
the controllers to the base class AbstractController.

src/mem/protocol/MESI_CMP_directory-L1cache.sm

@@ -126,7 +126,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
     bool isPresent(Address);
   }
 
-  TBETable L1_TBEs, template="<L1Cache_TBE>";
+  TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   MessageBuffer mandatoryQueue, ordered="false";
 

src/mem/protocol/MESI_CMP_directory-L2cache.sm

@@ -151,7 +151,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     bool isPresent(Address);
   }
 
-  TBETable L2_TBEs, template="<L2Cache_TBE>";
+  TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry a);
   void unset_cache_entry();

src/mem/protocol/MESI_CMP_directory-dir.sm

@@ -105,7 +105,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   // ** OBJECTS **
 
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   void set_tbe(TBE tbe);
   void unset_tbe();

src/mem/protocol/MI_example-cache.sm

@@ -98,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache")
 
 
   // STRUCTURES
-  TBETable TBEs, template="<L1Cache_TBE>";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   // PROTOTYPES
   void set_cache_entry(AbstractCacheEntry a);

src/mem/protocol/MI_example-dir.sm

@@ -102,7 +102,7 @@ machine(Directory, "Directory protocol")
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   void set_tbe(TBE b);
   void unset_tbe();

src/mem/protocol/MOESI_CMP_directory-L1cache.sm

@@ -142,7 +142,7 @@ machine(L1Cache, "Directory protocol")
 
   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 
-  TBETable TBEs, template="<L1Cache_TBE>";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
   TimerTable useTimerTable;
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 

src/mem/protocol/MOESI_CMP_directory-L2cache.sm

@@ -224,8 +224,7 @@ machine(L2Cache, "Token protocol")
     bool isTagPresent(Address);
   }
 
-
-  TBETable TBEs, template="<L2Cache_TBE>";
+  TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
   PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>";
 
   void set_cache_entry(AbstractCacheEntry b);

src/mem/protocol/MOESI_CMP_directory-dir.sm

@@ -1,4 +1,3 @@
-
 /*
  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
  * All rights reserved.
@@ -119,7 +118,7 @@ machine(Directory, "Directory protocol")
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   void set_tbe(TBE b);
   void unset_tbe();

src/mem/protocol/MOESI_CMP_directory-dma.sm

@@ -44,7 +44,7 @@ machine(DMA, "DMA Controller")
 
   MessageBuffer mandatoryQueue, ordered="false";
   MessageBuffer triggerQueue, ordered="true";
-  TBETable TBEs, template="<DMA_TBE>";
+  TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
   State cur_state;
 
   void set_tbe(TBE b);

src/mem/protocol/MOESI_CMP_token-L1cache.sm

@@ -180,7 +180,7 @@ machine(L1Cache, "Token protocol")
   void wakeUpAllBuffers();
   void wakeUpBuffers(Address a);
 
-  TBETable L1_TBEs, template="<L1Cache_TBE>";
+  TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 

src/mem/protocol/MOESI_CMP_token-dir.sm

@@ -157,7 +157,7 @@ machine(Directory, "Token protocol")
   PersistentTable persistentTable;
   TimerTable reissueTimerTable;
 
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   bool starving, default="false";
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";

src/mem/protocol/MOESI_hammer-cache.sm

@@ -173,7 +173,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     bool isPresent(Address);
   }
 
-  TBETable TBEs, template="<L1Cache_TBE>";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();

src/mem/protocol/MOESI_hammer-dir.sm

@@ -184,7 +184,7 @@ machine(Directory, "AMD Hammer-like protocol")
 
   Set fwd_set;
 
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
     Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);

src/mem/protocol/Network_test-cache.sm

@@ -66,25 +66,6 @@ machine(L1Cache, "Network_test L1 Cache")
     DataBlock DataBlk,       desc="Data in the block";
   }
 
-  // TBE fields
-  structure(TBE, desc="...") {
-    State TBEState,          desc="Transient state";
-    DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
-  }
-
-  structure(TBETable, external="yes") {
-    TBE lookup(Address);
-    void allocate(Address);
-    void deallocate(Address);
-    bool isPresent(Address);
-  }
-
-
-  // STRUCTURES
-
-  TBETable TBEs, template="<L1Cache_TBE>";
-
-
   // FUNCTIONS
 
   // cpu/testers/networktest/networktest.cc generates packets of the type
@@ -112,11 +93,11 @@ machine(L1Cache, "Network_test L1 Cache")
   }
 
 
-  State getState(TBE tbe, Entry cache_entry, Address addr) {
+  State getState(Entry cache_entry, Address addr) {
     return State:I;
   }
 
-  void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+  void setState(Entry cache_entry, Address addr, State state) {
 
   }
 
@@ -146,9 +127,7 @@ machine(L1Cache, "Network_test L1 Cache")
     if (mandatoryQueue_in.isReady()) {
       peek(mandatoryQueue_in, RubyRequest) {
         trigger(mandatory_request_type_to_event(in_msg.Type),
-                in_msg.LineAddress,
-                getCacheEntry(in_msg.LineAddress),
-                TBEs[in_msg.LineAddress]);
+                in_msg.LineAddress, getCacheEntry(in_msg.LineAddress));
       }
     }
   }

src/mem/protocol/RubySlicc_Exports.sm

@@ -31,6 +31,7 @@
 external_type(int, primitive="yes", default="0");
 external_type(bool, primitive="yes", default="false");
 external_type(std::string, primitive="yes");
+external_type(uint32_t, primitive="yes");
 external_type(uint64, primitive="yes");
 external_type(Time, primitive="yes", default="0");
 external_type(PacketPtr, primitive="yes");

src/mem/ruby/slicc_interface/AbstractController.cc

@@ -32,5 +32,11 @@
 AbstractController::AbstractController(const Params *p)
     : SimObject(p), Consumer(this)
 {
-  p->ruby_system->registerAbstractController(this);
+    m_version = p->version;
+    m_transitions_per_cycle = p->transitions_per_cycle;
+    m_buffer_size = p->buffer_size;
+    m_recycle_latency = p->recycle_latency;
+    m_number_of_TBEs = p->number_of_TBEs;
+    m_is_blocking = false;
+    p->ruby_system->registerAbstractController(this);
 }

src/mem/ruby/slicc_interface/AbstractController.hh

@@ -32,13 +32,14 @@
 #include <iostream>
 #include <string>
 
-#include "mem/packet.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
+#include "mem/ruby/system/MachineID.hh"
+#include "mem/packet.hh"
 #include "params/RubyController.hh"
 #include "sim/sim_object.hh"
 
@@ -82,6 +83,24 @@ class AbstractController : public SimObject, public Consumer
     //! Function for enqueuing a prefetch request
     virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
     { fatal("Prefetches not implemented!");}
+
+  protected:
+    int m_transitions_per_cycle;
+    int m_buffer_size;
+    int m_recycle_latency;
+    std::string m_name;
+    std::map<std::string, std::string> m_cfg;
+    NodeID m_version;
+    Network* m_net_ptr;
+    MachineID m_machineID;
+    bool m_is_blocking;
+    std::map<Address, MessageBuffer*> m_block_map;
+    typedef std::vector<MessageBuffer*> MsgVecType;
+    typedef std::map< Address, MsgVecType* > WaitingBufType;
+    WaitingBufType m_waiting_buffers;
+    int m_max_in_port_rank;
+    int m_cur_in_port_rank;
+    int m_number_of_TBEs;
 };
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__

src/mem/slicc/symbols/StateMachine.py

@@ -33,6 +33,7 @@ import slicc.generate.html as html
 import re
 
 python_class_map = {"int": "Int",
+                    "uint32_t" : "UInt32",
                     "std::string": "String",
                     "bool": "Bool",
                     "CacheMemory": "RubyCache",
@@ -261,7 +262,6 @@ class $c_ident : public AbstractController
     void wakeUpAllBuffers();
     void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
     void print(std::ostream& out) const;
-    void printConfig(std::ostream& out) const;
     void wakeup();
     void printStats(std::ostream& out) const;
     void clearStats();
@@ -285,8 +285,6 @@ private:
                 code('${{param.type_ast.type}} m_${{param.ident}};')
 
         code('''
-int m_number_of_TBEs;
-
 TransitionResult doTransition(${ident}_Event event,
 ''')
 
@@ -319,21 +317,6 @@ TransitionResult doTransitionWorker(${ident}_Event event,
         code('''
                                     const Address& addr);
 
-std::string m_name;
-int m_transitions_per_cycle;
-int m_buffer_size;
-int m_recycle_latency;
-std::map<std::string, std::string> m_cfg;
-NodeID m_version;
-Network* m_net_ptr;
-MachineID m_machineID;
-bool m_is_blocking;
-std::map<Address, MessageBuffer*> m_block_map;
-typedef std::vector<MessageBuffer*> MsgVecType;
-typedef std::map< Address, MsgVecType* > WaitingBufType;
-WaitingBufType m_waiting_buffers;
-int m_max_in_port_rank;
-int m_cur_in_port_rank;
 static ${ident}_ProfileDumper s_profileDumper;
 ${ident}_Profiler m_profiler;
 static int m_num_controllers;
@@ -465,12 +448,6 @@ stringstream ${ident}_transitionComment;
 $c_ident::$c_ident(const Params *p)
     : AbstractController(p)
 {
-    m_version = p->version;
-    m_transitions_per_cycle = p->transitions_per_cycle;
-    m_buffer_size = p->buffer_size;
-    m_recycle_latency = p->recycle_latency;
-    m_number_of_TBEs = p->number_of_TBEs;
-    m_is_blocking = false;
     m_name = "${ident}";
 ''')
         #
@@ -574,14 +551,9 @@ $c_ident::init()
                     elif var.ident.find("mandatoryQueue") < 0:
                         th = var.get("template", "")
                         expr = "%s  = new %s%s" % (vid, vtype.c_ident, th)
-
                         args = ""
                         if "non_obj" not in vtype and not vtype.isEnumeration:
-                            if expr.find("TBETable") >= 0:
-                                args = "m_number_of_TBEs"
-                            else:
-                                args = var.get("constructor_hack", "")
-
+                            args = var.get("constructor", "")
                         code('$expr($args);')
 
                     code('assert($vid != NULL);')
@@ -825,16 +797,6 @@ $c_ident::print(ostream& out) const
     out << "[$c_ident " << m_version << "]";
 }
 
-void
-$c_ident::printConfig(ostream& out) const
-{
-    out << "$c_ident config: " << m_name << endl;
-    out << "  version: " << m_version << endl;
-    map<string, string>::const_iterator it;
-    for (it = m_cfg.begin(); it != m_cfg.end(); it++)
-        out << "  " << it->first << ": " << it->second << endl;
-}
-
 void
 $c_ident::printStats(ostream& out) const
 {