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syscall_emul, riscv: add override keyword to RISCV Process class

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Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
This commit is contained in:
Brandon Potter
2017-05-15 14:03:20 -05:00
committed by Brandon Potter
parent 679a0e2ef1
commit 9aadcc7972
1 changed files with 6 additions and 4 deletions
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10
src/arch/riscv/process.hh
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@@ -48,17 +48,19 @@ class RiscvProcess : public Process
protected:
RiscvProcess(ProcessParams * params, ObjectFile *objFile);
void initState();
void initState() override;
template<class IntType>
void argsInit(int pageSize);
public:
RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
void setSyscallArg(ThreadContext *tc, int i,
RiscvISA::IntReg val) override;
void setSyscallReturn(ThreadContext *tc,
SyscallReturn return_value) override;
virtual bool mmapGrowsDown() const override { return false; }
};