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dev-arm: Implement System Security Control registers

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This block of system registers is part of the N1 SDP [1]

[1]: https://developer.arm.com/documentation/101489/0000/\
    Programmers-model/System-Security-Control-registers

Change-Id: I2ecf5cd247bd68eddcd359e91f3954070dbffaa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64951
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-09-29 14:56:56 +01:00
parent 4db981576e
commit 9a9de78811
4 changed files with 270 additions and 1 deletions
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src/dev/arm/SConscript
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@@ -54,7 +54,7 @@ SimObject('RealView.py', sim_objects=[
'GenericArmPciHost', 'RealViewCtrl', 'RealViewOsc',
'RealViewTemperatureSensor', 'AmbaFake', 'Pl011', 'Sp804', 'Sp805',
'GenericWatchdog', 'CpuLocalTimer', 'PL031', 'Pl050', 'Pl111', 'HDLcd',
'FVPBasePwrCtrl', 'RealView'],
'FVPBasePwrCtrl', 'RealView', 'SysSecCtrl'],
enums=['ArmPciIntRouting'], tags='arm isa')
SimObject('SMMUv3.py', sim_objects=['SMMUv3DeviceInterface', 'SMMUv3'],
tags='arm isa')
@@ -92,6 +92,7 @@ Source('smmu_v3_ports.cc', tags='arm isa');
Source('smmu_v3_proc.cc', tags='arm isa');
Source('smmu_v3_deviceifc.cc', tags='arm isa');
Source('smmu_v3_transl.cc', tags='arm isa');
Source('ssc.cc', tags='arm isa');
Source('timer_sp804.cc', tags='arm isa')
Source('watchdog_generic.cc', tags='arm isa')
Source('watchdog_sp805.cc', tags='arm isa')