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Registers: Collapse ARM and MIPS regfile directories.

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--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
This commit is contained in:
Gabe Black
2009-07-08 23:02:21 -07:00
parent aa031e1c11
commit 997f36c711
13 changed files with 140 additions and 212 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/SConscript
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@@ -41,7 +41,7 @@ if env['TARGET_ISA'] == 'arm':
Source('insts/static_inst.cc')
Source('isa.cc')
Source('pagetable.cc')
Source('regfile/regfile.cc')
Source('regfile.cc')
Source('tlb.cc')
Source('vtophys.cc')

2
src/arch/arm/isa.hh
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@@ -31,7 +31,7 @@
#ifndef __ARCH_ARM_ISA_HH__
#define __ARCH_MRM_ISA_HH__
#include "arch/arm/regfile/misc_regfile.hh"
#include "arch/arm/misc_regfile.hh"
#include "arch/arm/types.hh"
class Checkpoint;

0
src/arch/arm/regfile/misc_regfile.hh → src/arch/arm/misc_regfile.hh
View File

2
src/arch/arm/regfile/regfile.cc → src/arch/arm/regfile.cc
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@@ -28,7 +28,7 @@
* Authors: Stephen Hines
*/
#include "arch/arm/regfile/regfile.hh"
#include "arch/arm/regfile.hh"
#include "base/misc.hh"
#include "sim/serialize.hh"

72
src/arch/arm/regfile.hh
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@@ -28,9 +28,75 @@
* Authors: Stephen Hines
*/
#ifndef __ARCH_ARM_REGFILE_HH__
#define __ARCH_ARM_REGFILE_HH__
#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
#define __ARCH_ARM_REGFILE_REGFILE_HH__
#include "arch/arm/regfile/regfile.hh"
#include "arch/arm/types.hh"
#include "arch/arm/misc_regfile.hh"
#include "sim/faults.hh"
class Checkpoint;
class EventManager;
class ThreadContext;
namespace ArmISA
{
enum FPControlRegNums {
FIR = NumFloatArchRegs,
FCCR,
FEXR,
FENR,
FCSR
};
enum FCSRBits {
Inexact = 1,
Underflow,
Overflow,
DivideByZero,
Invalid,
Unimplemented
};
enum FCSRFields {
Flag_Field = 1,
Enable_Field = 6,
Cause_Field = 11
};
enum MiscIntRegNums {
zero_reg = NumIntArchRegs,
addr_reg,
rhi,
rlo,
r8_fiq, /* FIQ mode register bank */
r9_fiq,
r10_fiq,
r11_fiq,
r12_fiq,
r13_fiq, /* FIQ mode SP and LR */
r14_fiq,
r13_irq, /* IRQ mode SP and LR */
r14_irq,
r13_svc, /* SVC mode SP and LR */
r14_svc,
r13_undef, /* UNDEF mode SP and LR */
r14_undef,
r13_abt, /* ABT mode SP and LR */
r14_abt
};
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
} // namespace ArmISA
#endif

102
src/arch/arm/regfile/regfile.hh
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@@ -1,102 +0,0 @@
/*
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Stephen Hines
*/
#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
#define __ARCH_ARM_REGFILE_REGFILE_HH__
#include "arch/arm/types.hh"
#include "arch/arm/regfile/misc_regfile.hh"
#include "sim/faults.hh"
class Checkpoint;
class EventManager;
class ThreadContext;
namespace ArmISA
{
enum FPControlRegNums {
FIR = NumFloatArchRegs,
FCCR,
FEXR,
FENR,
FCSR
};
enum FCSRBits {
Inexact = 1,
Underflow,
Overflow,
DivideByZero,
Invalid,
Unimplemented
};
enum FCSRFields {
Flag_Field = 1,
Enable_Field = 6,
Cause_Field = 11
};
enum MiscIntRegNums {
zero_reg = NumIntArchRegs,
addr_reg,
rhi,
rlo,
r8_fiq, /* FIQ mode register bank */
r9_fiq,
r10_fiq,
r11_fiq,
r12_fiq,
r13_fiq, /* FIQ mode SP and LR */
r14_fiq,
r13_irq, /* IRQ mode SP and LR */
r14_irq,
r13_svc, /* SVC mode SP and LR */
r14_svc,
r13_undef, /* UNDEF mode SP and LR */
r14_undef,
r13_abt, /* ABT mode SP and LR */
r14_abt
};
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
} // namespace ArmISA
#endif

2
src/arch/mips/SConscript
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@@ -35,7 +35,7 @@ Import('*')
if env['TARGET_ISA'] == 'mips':
Source('faults.cc')
Source('isa.cc')
Source('regfile/misc_regfile.cc')
Source('misc_regfile.cc')
Source('tlb.cc')
Source('pagetable.cc')
Source('utility.cc')

2
src/arch/mips/isa.cc
View File

@@ -29,7 +29,7 @@
*/
#include "arch/mips/isa.hh"
#include "arch/mips/regfile/misc_regfile.hh"
#include "arch/mips/misc_regfile.hh"
#include "cpu/thread_context.hh"
namespace MipsISA

2
src/arch/mips/isa.hh
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@@ -31,7 +31,7 @@
#ifndef __ARCH_MIPS_ISA_HH__
#define __ARCH_MIPS_ISA_HH__
#include "arch/mips/regfile/misc_regfile.hh"
#include "arch/mips/misc_regfile.hh"
#include "arch/mips/types.hh"
class Checkpoint;

2
src/arch/mips/regfile/misc_regfile.cc → src/arch/mips/misc_regfile.cc
View File

@@ -32,7 +32,7 @@
#include "base/bitfield.hh"
#include "arch/mips/regfile/misc_regfile.hh"
#include "arch/mips/misc_regfile.hh"
#include "arch/mips/mt_constants.hh"
#include "arch/mips/pra_constants.hh"

0
src/arch/mips/regfile/misc_regfile.hh → src/arch/mips/misc_regfile.hh
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67
src/arch/mips/regfile.hh
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@@ -1,5 +1,6 @@
/*
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* Copyright (c) 2006 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,12 +26,72 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Gabe Black
* Authors: Korey Sewell
*/
#ifndef __ARCH_MIPS_REGFILE_HH__
#define __ARCH_MIPS_REGFILE_HH__
#include "arch/mips/regfile/regfile.hh"
#include <iostream>
#include <string>
#include "arch/mips/isa_traits.hh"
class BaseCPU;
class Checkpoint;
class EventManager;
namespace MipsISA
{
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
enum FPControlRegNums {
FIR = NumFloatArchRegs,
FCCR,
FEXR,
FENR,
FCSR
};
enum FCSRBits {
Inexact = 1,
Underflow,
Overflow,
DivideByZero,
Invalid,
Unimplemented
};
enum FCSRFields {
Flag_Field = 1,
Enable_Field = 6,
Cause_Field = 11
};
enum MiscIntRegNums {
LO = NumIntArchRegs,
HI,
DSPACX0,
DSPLo1,
DSPHi1,
DSPACX1,
DSPLo2,
DSPHi2,
DSPACX2,
DSPLo3,
DSPHi3,
DSPACX3,
DSPControl,
DSPLo0 = LO,
DSPHi0 = HI
};
//@TODO: Implementing ShadowSets needs to
//edit this value such that:
//TotalArchRegs = NumIntArchRegs * ShadowSets
const int TotalArchRegs = NumIntArchRegs;
} // namespace MipsISA
#endif

97
src/arch/mips/regfile/regfile.hh
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@@ -1,97 +0,0 @@
/*
* Copyright (c) 2006 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Korey Sewell
*/
#ifndef __ARCH_MIPS_REGFILE_REGFILE_HH__
#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include <iostream>
#include <string>
#include "arch/mips/isa_traits.hh"
class BaseCPU;
class Checkpoint;
class EventManager;
namespace MipsISA
{
const uint32_t MIPS32_QNAN = 0x7fbfffff;
const uint64_t MIPS64_QNAN = ULL(0x7fbfffffffffffff);
enum FPControlRegNums {
FIR = NumFloatArchRegs,
FCCR,
FEXR,
FENR,
FCSR
};
enum FCSRBits {
Inexact = 1,
Underflow,
Overflow,
DivideByZero,
Invalid,
Unimplemented
};
enum FCSRFields {
Flag_Field = 1,
Enable_Field = 6,
Cause_Field = 11
};
enum MiscIntRegNums {
LO = NumIntArchRegs,
HI,
DSPACX0,
DSPLo1,
DSPHi1,
DSPACX1,
DSPLo2,
DSPHi2,
DSPACX2,
DSPLo3,
DSPHi3,
DSPACX3,
DSPControl,
DSPLo0 = LO,
DSPHi0 = HI
};
//@TODO: Implementing ShadowSets needs to
//edit this value such that:
//TotalArchRegs = NumIntArchRegs * ShadowSets
const int TotalArchRegs = NumIntArchRegs;
} // namespace MipsISA
#endif