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arm: Mark some miscregs (timer counter) registers at unverifiable.

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The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
This commit is contained in:
Ali Saidi
2014-10-29 23:18:24 -05:00
parent e3ee27c7b4
commit 9900629f83
4 changed files with 619 additions and 610 deletions
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9
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -366,9 +366,12 @@ namespace Aarch64
if (miscReg == MISCREG_DC_ZVA_Xt && !read)
return new Dczva(machInst, rt, (IntRegIndex) miscReg, iss);
if (read)
return new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss);
else
if (read) {
StaticInstPtr si = new Mrs64(machInst, rt, (IntRegIndex) miscReg, iss);
if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
} else
return new Msr64(machInst, (IntRegIndex) miscReg, rt, iss);
} else if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
std::string full_mnem = csprintf("%s %s",

8
src/arch/arm/isa/formats/misc.isa
View File

@@ -273,8 +273,12 @@ let {{
if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
if (isRead)
return new Mrrc15(machInst, miscReg, rt2, rt, iss);
if (isRead) {
StaticInstPtr si = new Mrrc15(machInst, miscReg, rt2, rt, iss);
if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
}
return new Mcrr15(machInst, rt2, rt, miscReg, iss);
} else {
return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst,

1210
src/arch/arm/miscregs.cc
View File

File diff suppressed because it is too large Load Diff

2
src/arch/arm/miscregs.hh
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@@ -677,6 +677,8 @@ namespace ArmISA
enum MiscRegInfo {
MISCREG_IMPLEMENTED,
MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
// arch generic counter)
MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
// tells whether the instruction should raise a
// warning or fail