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--HG--
extra : convert_revision : 490f9909469751a6cdaf6669e4cd4589ce3a4093
This commit is contained in:
Gabe Black
2007-10-12 20:10:57 -07:00
parent ac27bc7878 0d6383b69e
commit 9660a0a552
46 changed files with 2576 additions and 82 deletions
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1
src/arch/x86/SConscript
View File

@@ -179,6 +179,7 @@ if env['TARGET_ISA'] == 'x86':
'general_purpose/system_calls.py',
'system/__init__.py',
'system/undefined_operation.py',
'system/msrs.py',
'simd128/__init__.py',
'simd128/integer/__init__.py',
'simd128/integer/data_transfer/__init__.py',

2
src/arch/x86/insts/microregop.cc
View File

@@ -66,7 +66,7 @@ namespace X86ISA
uint64_t _dest, uint64_t _src1, uint64_t _src2,
bool subtract) const
{
DPRINTF(Sparc, "flagMask = %#x\n", flagMask);
DPRINTF(X86, "flagMask = %#x\n", flagMask);
uint64_t flags = oldFlags & ~flagMask;
if(flagMask & (ECFBit | CFBit))
{

40
src/arch/x86/isa/decoder/one_byte_opcodes.isa
View File

@@ -325,27 +325,27 @@
default: lahf();
}
}
0x14: decode OPCODE_OP_BOTTOM3 {
0x0: mov_Al_Ob();
0x1: mov_rAX_Ov();
0x2: mov_Ob_Al();
0x3: mov_Ov_rAX();
0x4: StringInst::MOVS(Yb,Xb);
0x5: StringInst::MOVS(Yv,Xv);
0x6: StringTestInst::CMPS(Yb,Xb);
0x7: StringTestInst::CMPS(Yv,Xv);
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x0: Inst::TEST(rAb,Ib);
0x1: Inst::TEST(rAv,Iz);
0x2: StringInst::STOS(Yb);
0x3: StringInst::STOS(Yv);
0x4: lods_Al_Xb();
0x5: lods_rAX_Xv();
0x6: StringTestInst::SCAS(Yb);
0x7: StringTestInst::SCAS(Yv);
}
format Inst {
0x14: decode OPCODE_OP_BOTTOM3 {
0x0: MOV(rAb, Ob);
0x1: MOV(rAv, Ov);
0x2: MOV(Ob, rAb);
0x3: MOV(Ov, rAv);
0x4: StringInst::MOVS(Yb,Xb);
0x5: StringInst::MOVS(Yv,Xv);
0x6: StringTestInst::CMPS(Yb,Xb);
0x7: StringTestInst::CMPS(Yv,Xv);
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x0: TEST(rAb,Ib);
0x1: TEST(rAv,Iz);
0x2: StringInst::STOS(Yb);
0x3: StringInst::STOS(Yv);
0x4: StringInst::LODS(Xb);
0x5: StringInst::LODS(Xv);
0x6: StringTestInst::SCAS(Yb);
0x7: StringTestInst::SCAS(Yv);
}
0x16: MOV(Bb,Ib);
0x17: MOV(Bv,Iv);
0x18: decode OPCODE_OP_BOTTOM3 {

4
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View File

@@ -211,9 +211,9 @@
default: Inst::UD2();
}
0x06: decode OPCODE_OP_BOTTOM3 {
0x0: wrmsr();
0x0: Inst::WRMSR();
0x1: rdtsc();
0x2: rdmsr();
0x2: Inst::RDMSR();
0x3: rdpmc();
0x4: sysenter();
0x5: sysexit();

9
src/arch/x86/isa/formats/basic.isa
View File

@@ -147,12 +147,3 @@ def template BasicDecode {{
def template BasicDecodeWithMnemonic {{
return new %(class_name)s("%(mnemonic)s", machInst);
}};
// The most basic instruction format... used only for a few misc. insts
def format BasicOperate(code, *flags) {{
iop = InstObjParams(name, Name, 'SparcStaticInst', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = BasicExecute.subst(iop)
}};

10
src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
View File

@@ -59,6 +59,16 @@ microcode = '''
# Regular moves
#
def macroop MOV_R_MI {
limm t1, imm
ld reg, seg, [1, t0, t1]
};
def macroop MOV_MI_R {
limm t1, imm
st reg, seg, [1, t0, t1]
};
def macroop MOV_R_R {
mov reg, reg, regm
};

42
src/arch/x86/isa/insts/general_purpose/string/load_string.py
View File

@@ -53,16 +53,32 @@
#
# Authors: Gabe Black
microcode = ""
#let {{
# class LODS(Inst):
# "GenFault ${new UnimpInstFault}"
# class LODSB(Inst):
# "GenFault ${new UnimpInstFault}"
# class LODSW(Inst):
# "GenFault ${new UnimpInstFault}"
# class LODSD(Inst):
# "GenFault ${new UnimpInstFault}"
# class LODSQ(Inst):
# "GenFault ${new UnimpInstFault}"
#}};
microcode = '''
def macroop LODS_M {
# Find the constant we need to either add or subtract from rdi
ruflag t0, 10
movi t3, t3, dsz, flags=(CEZF,), dataSize=asz
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
ld rax, seg, [1, t0, rdi]
add rdi, rdi, t3, dataSize=asz
};
def macroop LODS_E_M {
# Find the constant we need to either add or subtract from rdi
ruflag t0, 10
movi t3, t3, dsz, flags=(CEZF,), dataSize=asz
subi t4, t0, dsz, dataSize=asz
mov t3, t3, t4, flags=(nCEZF,), dataSize=asz
topOfLoop:
ld rax, seg, [1, t0, rdi]
subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
add rdi, rdi, t3, dataSize=asz
bri t0, label("topOfLoop"), flags=(nCEZF,)
fault "NoFault"
};
'''

3
src/arch/x86/isa/insts/system/__init__.py
View File

@@ -53,7 +53,8 @@
#
# Authors: Gabe Black
categories = ["undefined_operation"]
categories = ["undefined_operation",
"msrs"]
microcode = ""
for category in categories:

74
src/arch/x86/isa/insts/system/msrs.py Normal file
View File

@@ -0,0 +1,74 @@
# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
# following conditions are met:
#
# The software must be used only for Non-Commercial Use which means any
# use which is NOT directed to receiving any direct monetary
# compensation for, or commercial advantage from such use. Illustrative
# examples of non-commercial use are academic research, personal study,
# teaching, education and corporate research & development.
# Illustrative examples of commercial use are distributing products for
# commercial advantage and providing services using the software for
# commercial advantage.
#
# If you wish to use this software or functionality therein that may be
# covered by patents for commercial use, please contact:
# Director of Intellectual Property Licensing
# Office of Strategy and Technology
# Hewlett-Packard Company
# 1501 Page Mill Road
# Palo Alto, California 94304
#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer. Redistributions
# in binary form must reproduce the above copyright notice, this list of
# conditions and the following disclaimer in the documentation and/or
# other materials provided with the distribution. Neither the name of
# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission. No right of
# sublicense is granted herewith. Derivatives of the software and
# output created using the software may be prepared, but only for
# Non-Commercial Uses. Derivatives of the software may be shared with
# others provided: (i) the others agree to abide by the list of
# conditions herein which includes the Non-Commercial Use restrictions;
# and (ii) such Derivatives of the software include the above copyright
# notice to acknowledge the contribution from this software where
# applicable, this list of conditions and the disclaimer below.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black
microcode = '''
def macroop WRMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
ld t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
mov rax, rax, t2, dataSize=4
srli t2, t2, 32, dataSize=8
mov rdx, rdx, t2, dataSize=4
};
def macroop RDMSR
{
limm t1, "IntAddrPrefixMSR >> 3"
mov t2, t2, rdx, dataSize=4
slli t2, t2, 32, dataSize=8
mov t2, t2, rax, dataSize=4
st t2, intseg, [8, t1, rcx], dataSize=8, addressSize=4
};
'''

4
src/arch/x86/isa/microasm.isa
View File

@@ -106,6 +106,10 @@ let {{
assembler.symbols["riprel"] = \
["1", assembler.symbols["t0"], assembler.symbols["t7"]]
# This segment selects an internal address space mapped to MSRs,
# CPUID info, etc.
assembler.symbols["intseg"] = "NUM_SEGMENTREGS"
for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()

22
src/arch/x86/isa/microops/ldstop.isa
View File

@@ -325,13 +325,13 @@ def template MicroLdStOpConstructor {{
let {{
class LdStOp(X86Microop):
def __init__(self, data, segment, addr, disp, dataSize):
def __init__(self, data, segment, addr, disp, dataSize, addressSize):
self.data = data
[self.scale, self.index, self.base] = addr
self.disp = disp
self.segment = segment
self.dataSize = dataSize
self.addressSize = "env.addressSize"
self.addressSize = addressSize
def getAllocator(self, *microFlags):
allocator = '''new %(class_name)s(machInst, mnemonic
@@ -378,10 +378,10 @@ let {{
exec_output += MicroLoadCompleteAcc.subst(iop)
class LoadOp(LdStOp):
def __init__(self, data, segment, addr,
disp = 0, dataSize="env.dataSize"):
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize", addressSize="env.addressSize"):
super(LoadOp, self).__init__(data, segment,
addr, disp, dataSize)
addr, disp, dataSize, addressSize)
self.className = Name
self.mnemonic = name
@@ -411,10 +411,10 @@ let {{
exec_output += MicroStoreCompleteAcc.subst(iop)
class StoreOp(LdStOp):
def __init__(self, data, segment, addr,
disp = 0, dataSize="env.dataSize"):
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize", addressSize="env.addressSize"):
super(StoreOp, self).__init__(data, segment,
addr, disp, dataSize)
addr, disp, dataSize, addressSize)
self.className = Name
self.mnemonic = name
@@ -432,10 +432,10 @@ let {{
exec_output += MicroLeaExecute.subst(iop)
class LeaOp(LdStOp):
def __init__(self, data, segment, addr,
disp = 0, dataSize="env.dataSize"):
def __init__(self, data, segment, addr, disp = 0,
dataSize="env.dataSize", addressSize="env.addressSize"):
super(LeaOp, self).__init__(data, segment,
addr, disp, dataSize)
addr, disp, dataSize, addressSize)
self.className = "Lea"
self.mnemonic = "lea"

3
src/arch/x86/isa/specialize.isa
View File

@@ -172,6 +172,9 @@ let {{
elif opType.tag in ("I", "J"):
# Immediates
Name += "_I"
elif opType.tag == "O":
# Immediate containing a memory offset
Name += "_MI"
elif opType.tag in ("PR", "R", "VR"):
# Non register modrm settings should cause an error
env.addReg(ModRMRMIndex)

2
src/arch/x86/miscregs.hh
View File

@@ -164,7 +164,7 @@ namespace X86ISA
MISCREG_MTRR_FIX_16K_80000,
MISCREG_MTRR_FIX_16K_A0000,
MISCREG_MTRR_FIX_4K_C0000,
MISCREG_MTRR_FIX_4k_C8000,
MISCREG_MTRR_FIX_4K_C8000,
MISCREG_MTRR_FIX_4K_D0000,
MISCREG_MTRR_FIX_4K_D8000,
MISCREG_MTRR_FIX_4K_E0000,

5
src/arch/x86/mmaped_ipr.hh
View File

@@ -76,7 +76,7 @@ namespace X86ISA
#if !FULL_SYSTEM
panic("Shouldn't have a memory mapped register in SE\n");
#else
panic("Memory mapped registers aren't implemented for x86!\n");
pkt->set(xc->readMiscReg(pkt->getAddr() / sizeof(MiscReg)));
#endif
}
@@ -86,7 +86,8 @@ namespace X86ISA
#if !FULL_SYSTEM
panic("Shouldn't have a memory mapped register in SE\n");
#else
panic("Memory mapped registers aren't implemented for x86!\n");
xc->setMiscReg(pkt->getAddr() / sizeof(MiscReg),
gtoh(pkt->get<uint64_t>()));
#endif
}
};

299
src/arch/x86/tlb.cc
View File

@@ -61,6 +61,7 @@
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
#include "arch/x86/x86_traits.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/thread_context.hh"
@@ -142,10 +143,304 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
uint32_t flags = req->getFlags();
bool storeCheck = flags & StoreCheck;
int seg = flags & (mask(NUM_SEGMENTREGS));
int seg = flags & mask(3);
//XXX Junk code to surpress the warning
if (storeCheck) seg = seg;
if (storeCheck);
// If this is true, we're dealing with a request to read an internal
// value.
if (seg == NUM_SEGMENTREGS) {
Addr prefix = vaddr & IntAddrPrefixMask;
if (prefix == IntAddrPrefixCPUID) {
panic("CPUID memory space not yet implemented!\n");
} else if (prefix == IntAddrPrefixMSR) {
req->setMmapedIpr(true);
Addr regNum = 0;
switch (vaddr & ~IntAddrPrefixMask) {
case 0x10:
regNum = MISCREG_TSC;
break;
case 0xFE:
regNum = MISCREG_MTRRCAP;
break;
case 0x174:
regNum = MISCREG_SYSENTER_CS;
break;
case 0x175:
regNum = MISCREG_SYSENTER_ESP;
break;
case 0x176:
regNum = MISCREG_SYSENTER_EIP;
break;
case 0x179:
regNum = MISCREG_MCG_CAP;
break;
case 0x17A:
regNum = MISCREG_MCG_STATUS;
break;
case 0x17B:
regNum = MISCREG_MCG_CTL;
break;
case 0x1D9:
regNum = MISCREG_DEBUG_CTL_MSR;
break;
case 0x1DB:
regNum = MISCREG_LAST_BRANCH_FROM_IP;
break;
case 0x1DC:
regNum = MISCREG_LAST_BRANCH_TO_IP;
break;
case 0x1DD:
regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
break;
case 0x1DE:
regNum = MISCREG_LAST_EXCEPTION_TO_IP;
break;
case 0x200:
regNum = MISCREG_MTRR_PHYS_BASE_0;
break;
case 0x201:
regNum = MISCREG_MTRR_PHYS_MASK_0;
break;
case 0x202:
regNum = MISCREG_MTRR_PHYS_BASE_1;
break;
case 0x203:
regNum = MISCREG_MTRR_PHYS_MASK_1;
break;
case 0x204:
regNum = MISCREG_MTRR_PHYS_BASE_2;
break;
case 0x205:
regNum = MISCREG_MTRR_PHYS_MASK_2;
break;
case 0x206:
regNum = MISCREG_MTRR_PHYS_BASE_3;
break;
case 0x207:
regNum = MISCREG_MTRR_PHYS_MASK_3;
break;
case 0x208:
regNum = MISCREG_MTRR_PHYS_BASE_4;
break;
case 0x209:
regNum = MISCREG_MTRR_PHYS_MASK_4;
break;
case 0x20A:
regNum = MISCREG_MTRR_PHYS_BASE_5;
break;
case 0x20B:
regNum = MISCREG_MTRR_PHYS_MASK_5;
break;
case 0x20C:
regNum = MISCREG_MTRR_PHYS_BASE_6;
break;
case 0x20D:
regNum = MISCREG_MTRR_PHYS_MASK_6;
break;
case 0x20E:
regNum = MISCREG_MTRR_PHYS_BASE_7;
break;
case 0x20F:
regNum = MISCREG_MTRR_PHYS_MASK_7;
break;
case 0x250:
regNum = MISCREG_MTRR_FIX_64K_00000;
break;
case 0x258:
regNum = MISCREG_MTRR_FIX_16K_80000;
break;
case 0x259:
regNum = MISCREG_MTRR_FIX_16K_A0000;
break;
case 0x268:
regNum = MISCREG_MTRR_FIX_4K_C0000;
break;
case 0x269:
regNum = MISCREG_MTRR_FIX_4K_C8000;
break;
case 0x26A:
regNum = MISCREG_MTRR_FIX_4K_D0000;
break;
case 0x26B:
regNum = MISCREG_MTRR_FIX_4K_D8000;
break;
case 0x26C:
regNum = MISCREG_MTRR_FIX_4K_E0000;
break;
case 0x26D:
regNum = MISCREG_MTRR_FIX_4K_E8000;
break;
case 0x26E:
regNum = MISCREG_MTRR_FIX_4K_F0000;
break;
case 0x26F:
regNum = MISCREG_MTRR_FIX_4K_F8000;
break;
case 0x277:
regNum = MISCREG_PAT;
break;
case 0x2FF:
regNum = MISCREG_DEF_TYPE;
break;
case 0x400:
regNum = MISCREG_MC0_CTL;
break;
case 0x404:
regNum = MISCREG_MC1_CTL;
break;
case 0x408:
regNum = MISCREG_MC2_CTL;
break;
case 0x40C:
regNum = MISCREG_MC3_CTL;
break;
case 0x410:
regNum = MISCREG_MC4_CTL;
break;
case 0x401:
regNum = MISCREG_MC0_STATUS;
break;
case 0x405:
regNum = MISCREG_MC1_STATUS;
break;
case 0x409:
regNum = MISCREG_MC2_STATUS;
break;
case 0x40D:
regNum = MISCREG_MC3_STATUS;
break;
case 0x411:
regNum = MISCREG_MC4_STATUS;
break;
case 0x402:
regNum = MISCREG_MC0_ADDR;
break;
case 0x406:
regNum = MISCREG_MC1_ADDR;
break;
case 0x40A:
regNum = MISCREG_MC2_ADDR;
break;
case 0x40E:
regNum = MISCREG_MC3_ADDR;
break;
case 0x412:
regNum = MISCREG_MC4_ADDR;
break;
case 0x403:
regNum = MISCREG_MC0_MISC;
break;
case 0x407:
regNum = MISCREG_MC1_MISC;
break;
case 0x40B:
regNum = MISCREG_MC2_MISC;
break;
case 0x40F:
regNum = MISCREG_MC3_MISC;
break;
case 0x413:
regNum = MISCREG_MC4_MISC;
break;
case 0xC0000080:
regNum = MISCREG_EFER;
break;
case 0xC0000081:
regNum = MISCREG_STAR;
break;
case 0xC0000082:
regNum = MISCREG_LSTAR;
break;
case 0xC0000083:
regNum = MISCREG_CSTAR;
break;
case 0xC0000084:
regNum = MISCREG_SF_MASK;
break;
case 0xC0000100:
regNum = MISCREG_FS_BASE;
break;
case 0xC0000101:
regNum = MISCREG_GS_BASE;
break;
case 0xC0000102:
regNum = MISCREG_KERNEL_GS_BASE;
break;
case 0xC0000103:
regNum = MISCREG_TSC_AUX;
break;
case 0xC0010000:
regNum = MISCREG_PERF_EVT_SEL0;
break;
case 0xC0010001:
regNum = MISCREG_PERF_EVT_SEL1;
break;
case 0xC0010002:
regNum = MISCREG_PERF_EVT_SEL2;
break;
case 0xC0010003:
regNum = MISCREG_PERF_EVT_SEL3;
break;
case 0xC0010004:
regNum = MISCREG_PERF_EVT_CTR0;
break;
case 0xC0010005:
regNum = MISCREG_PERF_EVT_CTR1;
break;
case 0xC0010006:
regNum = MISCREG_PERF_EVT_CTR2;
break;
case 0xC0010007:
regNum = MISCREG_PERF_EVT_CTR3;
break;
case 0xC0010010:
regNum = MISCREG_SYSCFG;
break;
case 0xC0010016:
regNum = MISCREG_IORR_BASE0;
break;
case 0xC0010017:
regNum = MISCREG_IORR_BASE1;
break;
case 0xC0010018:
regNum = MISCREG_IORR_MASK0;
break;
case 0xC0010019:
regNum = MISCREG_IORR_MASK1;
break;
case 0xC001001A:
regNum = MISCREG_TOP_MEM;
break;
case 0xC001001D:
regNum = MISCREG_TOP_MEM2;
break;
case 0xC0010114:
regNum = MISCREG_VM_CR;
break;
case 0xC0010115:
regNum = MISCREG_IGNNE;
break;
case 0xC0010116:
regNum = MISCREG_SMM_CTL;
break;
case 0xC0010117:
regNum = MISCREG_VM_HSAVE_PA;
break;
default:
return new GeneralProtection(0);
}
//The index is multiplied by the size of a MiscReg so that
//any memory dependence calculations will not see these as
//overlapping.
req->setPaddr(regNum * sizeof(MiscReg));
return NoFault;
} else {
panic("Access to unrecognized internal address space %#x.\n",
prefix);
}
}
// Get cr0. This will tell us how to do translation. We'll assume it was
// verified to be correct and consistent when set.

6
src/arch/x86/x86_traits.hh
View File

@@ -55,6 +55,8 @@
* Authors: Gabe Black
*/
#include "sim/host.hh"
#ifndef __ARCH_X86_X86TRAITS_HH__
#define __ARCH_X86_X86TRAITS_HH__
@@ -80,6 +82,10 @@ namespace X86ISA
const int NumSegments = 6;
const int NumSysSegments = 4;
const Addr IntAddrPrefixMask = ULL(0xffffffff00000000);
const Addr IntAddrPrefixCPUID = ULL(0x100000000);
const Addr IntAddrPrefixMSR = ULL(0x200000000);
}
#endif //__ARCH_X86_X86TRAITS_HH__

79
tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@@ -0,0 +1,79 @@
[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
clock=500
cpu_id=0
defer_registration=false
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
size=64
[system.cpu.itb]
type=X86ITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic
egid=100
env=
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]

18
tests/long/00.gzip/ref/x86/linux/simple-atomic/m5stats.txt Normal file
View File

@@ -0,0 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1268236 # Simulator instruction rate (inst/s)
host_mem_usage 175732 # Number of bytes of host memory used
host_seconds 1266.17 # Real time elapsed on the host
host_tick_rate 755026846 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1605801513 # Number of instructions simulated
sim_seconds 0.955992 # Number of seconds simulated
sim_ticks 955992360500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1911984722 # number of cpu cycles simulated
system.cpu.num_insts 1605801513 # Number of instructions executed
system.cpu.num_refs 607157396 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------

6
tests/long/00.gzip/ref/x86/linux/simple-atomic/stderr Normal file
View File

@@ -0,0 +1,6 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: instruction 'rdtsc' unimplemented
warn: Increasing stack size by one page.

44
tests/long/00.gzip/ref/x86/linux/simple-atomic/stdout Normal file
View File

@@ -0,0 +1,44 @@
spec_init
Loading Input Data
Duplicating 262144 bytes
Duplicating 524288 bytes
Input data 1048576 bytes in length
Compressing Input Data, level 1
Compressed data 108074 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 3
Compressed data 97831 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 5
Compressed data 83382 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 7
Compressed data 76606 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 73189 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 12 2007 10:09:31
M5 started Fri Oct 12 10:23:41 2007
M5 executing on nacho
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-atomic tests/run.py long/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 955992360500 because target called exit()

79
tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@@ -0,0 +1,79 @@
[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
clock=500
cpu_id=0
defer_registration=false
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
size=64
[system.cpu.itb]
type=X86ITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic
egid=100
env=
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:268435455
zero=false
port=system.membus.port[0]

18
tests/long/10.mcf/ref/x86/linux/simple-atomic/m5stats.txt Normal file
View File

@@ -0,0 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1236188 # Simulator instruction rate (inst/s)
host_mem_usage 310236 # Number of bytes of host memory used
host_seconds 224.96 # Real time elapsed on the host
host_tick_rate 755369641 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 278095687 # Number of instructions simulated
sim_seconds 0.169930 # Number of seconds simulated
sim_ticks 169929975000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 339859951 # number of cpu cycles simulated
system.cpu.num_insts 278095687 # Number of instructions executed
system.cpu.num_refs 124052668 # Number of memory references
system.cpu.workload.PROG:num_syscalls 429 # Number of system calls
---------- End Simulation Statistics ----------

999
tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out Normal file
View File

@@ -0,0 +1,999 @@
()
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497
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328
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426
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***
256
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***
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()
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***
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()
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***
183
()
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()
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***
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***
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()
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()
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()
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***
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()
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***
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()
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***
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()
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***
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()
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***
100
()
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***
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()
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***
74
()
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***
258
()
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***
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()
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***
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()
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()
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***
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()
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***
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()
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***
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()
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***
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()
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***
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()
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***
72
***
247
()
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***
86
()
24
***
82
()
23
***
87
***
117
()
22
***
76
***
119
()
21
***
84
()
20
***
78
()
19
***
73
()
18
***
81
()
17
***
65
()
16
***
63
***
101
()
15
***
71
()
14
***
75
()
13
***
322
()
12
***
77
()
11
***
283
()
10
***
79
()
9
***
145
***
150
()
8
***
67
()
7
***
60
***
231
()
6
***
56
***
234
()
5
***
164
***
202
()
4
***
53
()
3
***
130
***
185
***
200
()
2
***
205
()
1
***
39
***
95

5
tests/long/10.mcf/ref/x86/linux/simple-atomic/stderr Normal file
View File

@@ -0,0 +1,5 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: instruction 'rdtsc' unimplemented

29
tests/long/10.mcf/ref/x86/linux/simple-atomic/stdout Normal file
View File

@@ -0,0 +1,29 @@
MCF SPEC version 1.6.I
by Andreas Loebel
Copyright (c) 1998,1999 ZIB Berlin
All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
flow value : 4990014995
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 12 2007 10:09:31
M5 started Fri Oct 12 10:09:33 2007
M5 executing on nacho
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-atomic tests/run.py long/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 169929975000 because target called exit()

1
tests/long/10.mcf/test.py
View File

@@ -31,3 +31,4 @@ from cpu2000 import mcf
workload = mcf(isa, opsys, 'smred')
root.system.cpu.workload = workload.makeLiveProcess()
root.system.physmem.range=AddrRange('256MB')

79
tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@@ -0,0 +1,79 @@
[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
clock=500
cpu_id=0
defer_registration=false
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
size=64
[system.cpu.itb]
type=X86ITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic
egid=100
env=
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]

18
tests/long/20.parser/ref/x86/linux/simple-atomic/m5stats.txt Normal file
View File

@@ -0,0 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 892072 # Simulator instruction rate (inst/s)
host_mem_usage 179660 # Number of bytes of host memory used
host_seconds 1699.28 # Real time elapsed on the host
host_tick_rate 517205729 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1515877384 # Number of instructions simulated
sim_seconds 0.878876 # Number of seconds simulated
sim_ticks 878876322500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 1757752646 # number of cpu cycles simulated
system.cpu.num_insts 1515877384 # Number of instructions executed
system.cpu.num_refs 533543283 # Number of memory references
system.cpu.workload.PROG:num_syscalls 541 # Number of system calls
---------- End Simulation Statistics ----------

8
tests/long/20.parser/ref/x86/linux/simple-atomic/stderr Normal file
View File

@@ -0,0 +1,8 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: instruction 'rdtsc' unimplemented
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.

72
tests/long/20.parser/ref/x86/linux/simple-atomic/stdout Normal file
View File

@@ -0,0 +1,72 @@
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
Welcome to the Link Parser -- Version 2.1
Copyright (C) 1991-1995 Daniel Sleator and Davy Temperley
Processing sentences in batch mode
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
* I thought terrible after our discussion
* I wonder how much money have you earned
* Janet who is an expert on dogs helped me choose one
* she interviewed more programmers than was hired
* such flowers are found chiefly particularly in Europe
* the dogs some of which were very large ran after the man
* the man whom I play tennis is here
* there is going to be an important meeting January
* to pretend that our program is usable in its current form would be happy
* we're thinking about going to a movie this theater
* which dog you said you chased
- also invited to the meeting were several prominent scientists
- he ran home so quickly that his mother could hardly believe he had called from school
- so many people attended that they spilled over into several neighboring fields
- voting in favor of the bill were 36 Republicans and 4 moderate Democrats
: Grace may not be possible to fix the problem
any program as good as ours should be useful
biochemically , I think the experiment has a lot of problems
Fred has had five years of experience as a programmer
he is looking for another job
how did John do it
how many more people do you think will come
how much more spilled
I have more money than John has time
I made it clear that I was angry
I wonder how John did it
I wonder how much more quickly he ran
invite John and whoever else you want to invite
it is easier to ignore the problem than it is to solve it
many who initially supported Thomas later changed their minds
neither Mary nor Louise are coming to the party
she interviewed more programmers than were hired
telling Joe that Sue was coming to the party would create a real problem
the man with whom I play tennis is here
there is a dog in the park
this is not the man we know and love
we like to eat at restaurants , usually on weekends
what did John say he thought you should do
about 2 million people attended
the five best costumes got prizes
No errors!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 12 2007 10:09:31
M5 started Fri Oct 12 12:42:44 2007
M5 executing on nacho
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-atomic tests/run.py long/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 878876322500 because target called exit()

79
tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@@ -0,0 +1,79 @@
[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
clock=500
cpu_id=0
defer_registration=false
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
size=64
[system.cpu.itb]
type=X86ITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic
egid=100
env=
euid=100
executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]

18
tests/long/70.twolf/ref/x86/linux/simple-atomic/m5stats.txt Normal file
View File

@@ -0,0 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 1236095 # Simulator instruction rate (inst/s)
host_mem_usage 183352 # Number of bytes of host memory used
host_seconds 177.93 # Real time elapsed on the host
host_tick_rate 734446997 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 219936106 # Number of instructions simulated
sim_seconds 0.130679 # Number of seconds simulated
sim_ticks 130679026000 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 261358053 # number of cpu cycles simulated
system.cpu.num_insts 219936106 # Number of instructions executed
system.cpu.num_refs 77164404 # Number of memory references
system.cpu.workload.PROG:num_syscalls 395 # Number of system calls
---------- End Simulation Statistics ----------

276
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out Normal file
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@@ -0,0 +1,276 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin Normal file
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@@ -0,0 +1,17 @@
$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 Normal file
View File

@@ -0,0 +1,11 @@
$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 Normal file
View File

@@ -0,0 +1,2 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav Normal file
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@@ -0,0 +1,18 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 Normal file
View File

@@ -0,0 +1,19 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf Normal file
View File

@@ -0,0 +1,29 @@
net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

7
tests/long/70.twolf/ref/x86/linux/simple-atomic/stderr Normal file
View File

@@ -0,0 +1,7 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: instruction 'rdtsc' unimplemented
warn: Increasing stack size by one page.
warn: Increasing stack size by one page.

28
tests/long/70.twolf/ref/x86/linux/simple-atomic/stdout Normal file
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@@ -0,0 +1,28 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 12 2007 09:55:57
M5 started Fri Oct 12 09:59:28 2007
M5 executing on nacho
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic tests/run.py long/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sav
Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-atomic/smred.sv2
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 130679026000 because target called exit()

79
tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini Normal file
View File

@@ -0,0 +1,79 @@
[root]
type=Root
children=system
dummy=0
[system]
type=System
children=cpu membus physmem
mem_mode=atomic
physmem=system.physmem
[system.cpu]
type=AtomicSimpleCPU
children=dtb itb tracer workload
clock=500
cpu_id=0
defer_registration=false
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
phase=0
progress_interval=0
simulate_stalls=false
system=system
tracer=system.cpu.tracer
width=1
workload=system.cpu.workload
dcache_port=system.membus.port[2]
icache_port=system.membus.port[1]
[system.cpu.dtb]
type=X86DTB
size=64
[system.cpu.itb]
type=X86ITB
size=64
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
euid=100
executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
output=cout
pid=100
ppid=99
system=system
uid=100
[system.membus]
type=Bus
block_size=64
bus_id=0
clock=1000
responder_set=false
width=64
port=system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=PhysicalMemory
file=
latency=1
range=0:134217727
zero=false
port=system.membus.port[0]

18
tests/quick/00.hello/ref/x86/linux/simple-atomic/m5stats.txt Normal file
View File

@@ -0,0 +1,18 @@
---------- Begin Simulation Statistics ----------
host_inst_rate 66885 # Simulator instruction rate (inst/s)
host_mem_usage 172164 # Number of bytes of host memory used
host_seconds 0.13 # Real time elapsed on the host
host_tick_rate 38756587 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 8584 # Number of instructions simulated
sim_seconds 0.000005 # Number of seconds simulated
sim_ticks 4986500 # Number of ticks simulated
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.numCycles 9974 # number of cpu cycles simulated
system.cpu.num_insts 8584 # Number of instructions executed
system.cpu.num_refs 1765 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
---------- End Simulation Statistics ----------

5
tests/quick/00.hello/ref/x86/linux/simple-atomic/stderr Normal file
View File

@@ -0,0 +1,5 @@
0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
warn: instruction 'fnstcw_Mw' unimplemented
warn: instruction 'fldcw_Mw' unimplemented
warn: instruction 'rdtsc' unimplemented

14
tests/quick/00.hello/ref/x86/linux/simple-atomic/stdout Normal file
View File

@@ -0,0 +1,14 @@
Hello world!
M5 Simulator System
Copyright (c) 2001-2006
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Oct 12 2007 09:55:57
M5 started Fri Oct 12 09:56:08 2007
M5 executing on nacho
command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-atomic tests/run.py quick/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
Exiting @ tick 4986500 because target called exit()

57
util/qdo
View File

@@ -1,6 +1,6 @@
#! /usr/bin/env python
# Copyright (c) 2004-2005 The Regents of The University of Michigan
# Copyright (c) 2004-2005, 2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
@@ -27,6 +27,15 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Ali Saidi
# Important!
# This script expects a simple $ prompt, if you are using a shell other than
# sh which defaults to this you'll need to add something like the following
# to your bashrc/bash_profile script:
#if [ "$OAR_USER" = "xxxx" ]; then
# PS1='$ '
import sys
import os
@@ -46,13 +55,13 @@ optparser.add_option('-e', dest='stderr_file',
optparser.add_option('-o', dest='stdout_file',
help='command stdout output file')
optparser.add_option('-l', dest='save_log', action='store_true',
help='save qsub output log file')
help='save oarsub output log file')
optparser.add_option('-N', dest='job_name',
help='qsub job name')
help='oarsub job name')
optparser.add_option('-q', dest='dest_queue',
help='qsub destination queue')
optparser.add_option('--qwait', dest='qsub_timeout', type='int',
help='qsub queue wait timeout', default=30*60)
help='oarsub destination queue')
optparser.add_option('--qwait', dest='oarsub_timeout', type='int',
help='oarsub queue wait timeout', default=30*60)
optparser.add_option('-t', dest='cmd_timeout', type='int',
help='command execution timeout', default=600*60)
@@ -63,7 +72,7 @@ if cmd == []:
sys.exit(1)
# If we want to do this, need to add check here to make sure cmd[0] is
# a valid PBS job name, else qsub will die on us.
# a valid PBS job name, else oarsub will die on us.
#
#if not options.job_name:
# options.job_name = cmd[0]
@@ -98,11 +107,11 @@ class Shell(pexpect.spawn):
self.quick_timeout = 15
# wait for a prompt, then change it
try:
self.expect('\$ ', options.qsub_timeout)
self.expect('\$ ', options.oarsub_timeout)
except pexpect.TIMEOUT:
print >>sys.stderr, "%s: qsub timed out." % progname
print >>sys.stderr, "%s: oarsub timed out." % progname
self.kill(9)
self.close(wait=True)
self.safe_close()
sys.exit(1)
self.do_command('unset PROMPT_COMMAND; PS1="qdo$ "')
@@ -137,8 +146,17 @@ class Shell(pexpect.spawn):
(output, status) = shell.do_command('[ -d %s ]' % dirname,
self.quick_timeout)
return status == 0
# Don't actually try to close it.. just wait until it closes by itself
# We can't actually kill the pid which is what it's trying to do, and if
# we call wait we could be in an unfortunate situation of it printing input
# right as we call wait, so the input is never read and the process never ends
def safe_close(self):
count = 0
while self.isalive() and count < 10:
time.sleep(1)
self.close(force=False)
# Spawn the interactive pool job.
# Hack to do link on poolfs... disabled for now since
@@ -148,11 +166,12 @@ if False and len(cmd) > 50:
shell_cmd = 'ssh -t poolfs /bin/sh -l'
print "%s: running %s on poolfs" % (progname, cmd[0])
else:
shell_cmd = 'qsub -I -S /bin/sh'
shell_cmd = 'oarsub -I'
if options.job_name:
shell_cmd += ' -N "%s"' % options.job_name
shell_cmd += ' -n "%s"' % options.job_name
if options.dest_queue:
shell_cmd += ' -q ' + options.dest_queue
shell_cmd += ' -d %s' % cwd
shell = Shell(shell_cmd)
@@ -197,25 +216,23 @@ try:
except pexpect.TIMEOUT:
print >>sys.stderr, "%s: command timed out after %d seconds." \
% (progname, options.cmd_timeout)
shell.sendline('~.') # qsub/ssh termination escape sequence
shell.close(wait=True)
shell.sendline('~.') # oarsub/ssh termination escape sequence
shell.safe_close()
status = 3
if output:
print output
finally:
# end job
if shell.isalive():
shell.sendline('exit')
shell.expect('qsub: job .* completed\r\n')
shell.close(wait=True)
shell.expect('Disconnected from OAR job .*')
shell.safe_close()
# if there was an error, log the output even if not requested
if status != 0 or options.save_log:
log = file('qdo-log.' + str(os.getpid()), 'w')
log.write(shell.full_output)
log.close()
del shell
sys.exit(status)