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Fixed the priv instruction format.

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src/arch/sparc/isa/formats/priv.isa:
    Fix the priv format so that it uses isa_parser operands rather than accessing the registers directly in checkCode. Also, the expressions needed to be negated.
src/arch/sparc/isa/operands.isa:
    Added an Hpstate operand, and adjusted the numbering.

--HG--
extra : convert_revision : 4a70862df061aa9e1b9eab125c4c2fc839ac3b5a
This commit is contained in:
Gabe Black
2006-10-25 17:58:44 -04:00
parent 99d9d40e6c
commit 93b3176d4e
2 changed files with 13 additions and 13 deletions
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5
src/arch/sparc/isa/formats/priv.isa
View File

@@ -121,15 +121,14 @@ let {{
// Primary format for integer operate instructions:
def format Priv(code, *opt_flags) {{
checkCode = '''((xc->readMiscReg(PrStart + MISCREG_PSTATE))<2:2>) ||
((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)'''
checkCode = "!(Pstate<2:2> || Hpstate<2:2>)"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))
}};
def format HPriv(code, *opt_flags) {{
checkCode = "((xc->readMiscReg(HprStart + MISCREG_HPSTATE))<2:2>)"
checkCode = "!Hpstate<2:2>"
(header_output, decoder_output,
exec_output, decode_block) = doPrivFormat(code,
checkCode, name, Name, opt_flags + ('IprAccessOp',))

21
src/arch/sparc/isa/operands.isa
View File

@@ -95,18 +95,19 @@ def operands {{
'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 44),
'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 45),
'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 46),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 47),
'Hpstate': ('ControlReg', 'udw', 'MISCREG_HPSTATE', None, 47),
'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 48),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 48),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 49),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 50),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 51),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 52),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 53),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 54),
'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP', None, 49),
'Cansave': ('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 50),
'Canrestore': ('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 51),
'Cleanwin': ('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 52),
'Otherwin': ('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 53),
'Wstate': ('ControlReg', 'udw', 'MISCREG_WSTATE', None, 54),
'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 55),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 55),
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 56),
'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', None, 56),
'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 57),
# Mem gets a large number so it's always last
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)