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arch-arm: Merge checkFaultRead/Write into single checkFaultAccess

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Change-Id: I6b4b8a2ced53c3957a9f1d9b3ea51851a9ec7343
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61679
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-07-11 14:28:47 +01:00
parent 1666e6620a
commit 936f1e8603
3 changed files with 16 additions and 41 deletions
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32
src/arch/arm/isa/insts/data64.isa
View File

@@ -311,8 +311,14 @@ let {{
''')
msrMrs64EnabledCheckCode = '''
auto pre_flat = (MiscRegIndex)snsBankedIndex64(%s, xc->tcBase());
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(miscRegClass[pre_flat]).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
// Check for read/write access right
if (fault = checkFault%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr,
if (fault = checkFaultAccessAArch64SysReg(flat_idx, cpsr,
xc->tcBase(), *this); fault != NoFault) {
return fault;
}
@@ -321,24 +327,8 @@ let {{
if (fault != NoFault) return fault;
'''
msr_check_code = '''
auto pre_flat = (MiscRegIndex)snsBankedIndex64(dest, xc->tcBase());
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(miscRegClass[pre_flat]).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
''' % (msrMrs64EnabledCheckCode % ('Write'),)
mrs_check_code = '''
auto pre_flat = (MiscRegIndex)snsBankedIndex64(op1, xc->tcBase());
MiscRegIndex flat_idx = (MiscRegIndex) xc->tcBase()->
flattenRegId(miscRegClass[pre_flat]).index();
CPSR cpsr = Cpsr;
ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
%s
''' % (msrMrs64EnabledCheckCode % ('Read'),)
msr_check_code = msrMrs64EnabledCheckCode % 'dest'
mrs_check_code = msrMrs64EnabledCheckCode % 'op1'
mrsCode = mrs_check_code + '''
XDest = MiscOp1_ud;
@@ -553,8 +543,8 @@ let {{
mnemonic);
}
if (fault = checkFaultWriteAArch64SysReg(misc_index, Hcr64,
Scr64, Cpsr, xc->tcBase(), *this); fault != NoFault) {
if (fault = checkFaultAccessAArch64SysReg(misc_index,
Cpsr, xc->tcBase(), *this); fault != NoFault) {
return fault;
}

15
src/arch/arm/regs/misc.cc
View File

@@ -724,19 +724,8 @@ unflattenMiscReg(int reg)
}
Fault
checkFaultReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc, const MiscRegOp64 &inst)
{
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return inst.undefined();
return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
}
Fault
checkFaultWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc, const MiscRegOp64 &inst)
checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr,
ThreadContext *tc, const MiscRegOp64 &inst)
{
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))

10
src/arch/arm/regs/misc.hh
View File

@@ -2790,13 +2790,9 @@ namespace ArmISA
// Generic Timer system registers
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc);
// Checks read access permissions to AArch64 system registers
Fault checkFaultReadAArch64SysReg(MiscRegIndex reg, HCR hcr,
SCR scr, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst);
// Checks write access permissions to AArch64 system registers
Fault checkFaultWriteAArch64SysReg(MiscRegIndex reg, HCR hcr,
SCR scr, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst);
// Checks access permissions to AArch64 system registers
Fault checkFaultAccessAArch64SysReg(MiscRegIndex reg, CPSR cpsr,
ThreadContext *tc, const MiscRegOp64 &inst);
// Uses just the scr.ns bit to pre flatten the misc regs. This is useful
// for MCR/MRC instructions