mem: Fix whitespace in mem/ruby/system/Sequencer.py.
Some aspects of the formatting in this file were questionable, like aligning =s between adjacent lines, although not technically against the style rules as far as I know. More strangely though, the whole file used three space indents instead of the typical four. Change-Id: I7b60f1978c5b2c60a15296b10d09d5701cf7fa5c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52108 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
@@ -42,100 +42,100 @@ from m5.proxy import *
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from m5.objects.ClockedObject import ClockedObject
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class RubyPort(ClockedObject):
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type = 'RubyPort'
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abstract = True
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cxx_header = "mem/ruby/system/RubyPort.hh"
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cxx_class = 'gem5::ruby::RubyPort'
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type = 'RubyPort'
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abstract = True
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cxx_header = "mem/ruby/system/RubyPort.hh"
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cxx_class = 'gem5::ruby::RubyPort'
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version = Param.Int(0, "")
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version = Param.Int(0, "")
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in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
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"The CPU request ports should be connected to this. If a CPU "
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"has multiple ports (e.g., I/D ports) all of the ports for a "
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"single CPU can connect to one RubyPort.")
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slave = DeprecatedParam(in_ports,
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'`slave` is now called `in_ports`')
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in_ports = VectorResponsePort("CPU side of this RubyPort/Sequencer. "
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"The CPU request ports should be connected to this. If a CPU "
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"has multiple ports (e.g., I/D ports) all of the ports for a "
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"single CPU can connect to one RubyPort.")
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slave = DeprecatedParam(in_ports, '`slave` is now called `in_ports`')
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interrupt_out_port = VectorRequestPort("Port to connect to x86 interrupt "
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"controller to send the CPU requests from outside.")
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master = DeprecatedParam(interrupt_out_port,
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'`master` is now called `interrupt_out_port`')
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interrupt_out_port = VectorRequestPort("Port to connect to x86 interrupt "
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"controller to send the CPU requests from outside.")
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master = DeprecatedParam(interrupt_out_port,
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'`master` is now called `interrupt_out_port`')
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pio_request_port = RequestPort("Ruby pio request port")
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pio_master_port = DeprecatedParam(pio_request_port,
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'`pio_master_port` is now called `pio_request_port`')
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pio_request_port = RequestPort("Ruby pio request port")
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pio_master_port = DeprecatedParam(pio_request_port,
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'`pio_master_port` is now called `pio_request_port`')
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mem_request_port = RequestPort("Ruby mem request port")
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mem_master_port = DeprecatedParam(mem_request_port,
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'`mem_master_port` is now called `mem_request_port`')
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mem_request_port = RequestPort("Ruby mem request port")
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mem_master_port = DeprecatedParam(mem_request_port,
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'`mem_master_port` is now called `mem_request_port`')
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pio_response_port = ResponsePort("Ruby pio response port")
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pio_slave_port = DeprecatedParam(pio_response_port,
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'`pio_slave_port` is now called `pio_response_port`')
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pio_response_port = ResponsePort("Ruby pio response port")
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pio_slave_port = DeprecatedParam(pio_response_port,
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'`pio_slave_port` is now called `pio_response_port`')
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using_ruby_tester = Param.Bool(False, "")
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no_retry_on_stall = Param.Bool(False, "")
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ruby_system = Param.RubySystem(Parent.any, "")
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system = Param.System(Parent.any, "system object")
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support_data_reqs = Param.Bool(True, "data cache requests supported")
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support_inst_reqs = Param.Bool(True, "inst cache requests supported")
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is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
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using_ruby_tester = Param.Bool(False, "")
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no_retry_on_stall = Param.Bool(False, "")
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ruby_system = Param.RubySystem(Parent.any, "")
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system = Param.System(Parent.any, "system object")
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support_data_reqs = Param.Bool(True, "data cache requests supported")
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support_inst_reqs = Param.Bool(True, "inst cache requests supported")
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is_cpu_sequencer = Param.Bool(True, "connected to a cpu")
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class RubyPortProxy(RubyPort):
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type = 'RubyPortProxy'
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cxx_header = "mem/ruby/system/RubyPortProxy.hh"
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cxx_class = 'gem5::ruby::RubyPortProxy'
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type = 'RubyPortProxy'
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cxx_header = "mem/ruby/system/RubyPortProxy.hh"
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cxx_class = 'gem5::ruby::RubyPortProxy'
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class RubySequencer(RubyPort):
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type = 'RubySequencer'
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cxx_class = 'gem5::ruby::Sequencer'
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cxx_header = "mem/ruby/system/Sequencer.hh"
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type = 'RubySequencer'
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cxx_class = 'gem5::ruby::Sequencer'
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cxx_header = "mem/ruby/system/Sequencer.hh"
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dcache = Param.RubyCache("")
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dcache = Param.RubyCache("")
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max_outstanding_requests = Param.Int(16,
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"max requests (incl. prefetches) outstanding")
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deadlock_threshold = Param.Cycles(500000,
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"max outstanding cycles for a request before deadlock/livelock declared")
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garnet_standalone = Param.Bool(False, "")
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# id used by protocols that support multiple sequencers per controller
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# 99 is the dummy default value
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coreid = Param.Int(99, "CorePair core id")
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max_outstanding_requests = Param.Int(16,
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"max requests (incl. prefetches) outstanding")
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deadlock_threshold = Param.Cycles(500000,
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"max outstanding cycles for a request "
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"before deadlock/livelock declared")
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garnet_standalone = Param.Bool(False, "")
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# id used by protocols that support multiple sequencers per controller
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# 99 is the dummy default value
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coreid = Param.Int(99, "CorePair core id")
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def connectCpuPorts(self, cpu):
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"""
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Helper for connecting all cpu memory request output ports to this
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object's in_ports.
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This assumes the provided cpu object is an instance of BaseCPU. Non-cpu
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objects should use connectInstPort and connectDataPort.
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"""
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import m5.objects
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assert(isinstance(cpu, m5.objects.BaseCPU))
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# this connects all cpu mem-side ports to self.in_ports
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cpu.connectAllPorts(self)
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def connectCpuPorts(self, cpu):
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"""
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Helper for connecting all cpu memory request output ports to this
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object's in_ports.
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This assumes the provided cpu object is an instance of BaseCPU. Non-cpu
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objects should use connectInstPort and connectDataPort.
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"""
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import m5.objects
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assert(isinstance(cpu, m5.objects.BaseCPU))
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# this connects all cpu mem-side ports to self.in_ports
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cpu.connectAllPorts(self)
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def connectIOPorts(self, piobus):
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"""
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Helper for connecting this object's IO request and response ports to the
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provided bus object. Usually a iobus object is used to wireup IO
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components in a full system simulation. Incoming/Outgoing IO requests do
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not go though the SLICC protocol so the iobus must be connected to the
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sequencer directly.
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"""
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import m5.defines
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self.pio_request_port = piobus.cpu_side_ports
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self.mem_request_port = piobus.cpu_side_ports
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if m5.defines.buildEnv['TARGET_ISA'] == "x86":
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self.pio_response_port = piobus.mem_side_ports
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def connectIOPorts(self, piobus):
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"""
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Helper for connecting this object's IO request and response ports to
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the provided bus object. Usually a iobus object is used to wireup IO
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components in a full system simulation. Incoming/Outgoing IO requests
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do not go though the SLICC protocol so the iobus must be connected to
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the sequencer directly.
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"""
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import m5.defines
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self.pio_request_port = piobus.cpu_side_ports
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self.mem_request_port = piobus.cpu_side_ports
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if m5.defines.buildEnv['TARGET_ISA'] == "x86":
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self.pio_response_port = piobus.mem_side_ports
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class RubyHTMSequencer(RubySequencer):
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type = 'RubyHTMSequencer'
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cxx_class = 'gem5::ruby::HTMSequencer'
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cxx_header = "mem/ruby/system/HTMSequencer.hh"
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type = 'RubyHTMSequencer'
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cxx_class = 'gem5::ruby::HTMSequencer'
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cxx_header = "mem/ruby/system/HTMSequencer.hh"
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class DMASequencer(RubyPort):
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type = 'DMASequencer'
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cxx_header = "mem/ruby/system/DMASequencer.hh"
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cxx_class = 'gem5::ruby::DMASequencer'
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type = 'DMASequencer'
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cxx_header = "mem/ruby/system/DMASequencer.hh"
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cxx_class = 'gem5::ruby::DMASequencer'
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max_outstanding_requests = Param.Int(64, "max outstanding requests")
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max_outstanding_requests = Param.Int(64, "max outstanding requests")
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