arch-x86: Generalize the RegOp operands.
This mechanism can now be used in other types of microops. Change-Id: I82cb15b9d7b3c1e684aaa7482ea98b313f1d85d9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42345 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
203
src/arch/x86/insts/microop_args.hh
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203
src/arch/x86/insts/microop_args.hh
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@@ -0,0 +1,203 @@
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/*
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* Copyright 2021 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_X86_INSTS_MICROOP_ARGS_HH__
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#define __ARCH_X86_INSTS_MICROOP_ARGS_HH__
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#include <cstdint>
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#include <sstream>
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#include <string>
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#include "arch/x86/insts/static_inst.hh"
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#include "arch/x86/regs/int.hh"
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#include "arch/x86/types.hh"
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#include "base/cprintf.hh"
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#include "cpu/reg_class.hh"
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namespace X86ISA
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{
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struct DestOp
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{
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using ArgType = InstRegIndex;
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const RegIndex dest;
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const size_t size;
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RegIndex index() const { return dest; }
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DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
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};
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struct Src1Op
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{
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using ArgType = InstRegIndex;
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const RegIndex src1;
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const size_t size;
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RegIndex index() const { return src1; }
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Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
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};
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struct Src2Op
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{
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using ArgType = InstRegIndex;
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const RegIndex src2;
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const size_t size;
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RegIndex index() const { return src2; }
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Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
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};
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template <class Base>
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struct FoldedOp : public Base
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{
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template <class InstType>
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FoldedOp(InstType *inst, typename Base::ArgType idx) :
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Base(INTREG_FOLDED(idx.index(), inst->foldOBit), inst->dataSize)
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{}
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void
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print(std::ostream &os) const
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{
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X86StaticInst::printReg(os, RegId(IntRegClass, this->index()),
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this->size);
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}
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};
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template <class Base>
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struct CrOp : public Base
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{
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template <class InstType>
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CrOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(), 0) {}
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void
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print(std::ostream &os) const
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{
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ccprintf(os, "cr%d", this->index());
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}
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};
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template <class Base>
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struct DbgOp : public Base
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{
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template <class InstType>
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DbgOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(), 0) {}
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void
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print(std::ostream &os) const
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{
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ccprintf(os, "dr%d", this->index());
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}
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};
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template <class Base>
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struct SegOp : public Base
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{
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template <class InstType>
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SegOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(), 0) {}
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void
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print(std::ostream &os) const
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{
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X86StaticInst::printSegment(os, this->index());
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}
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};
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template <class Base>
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struct MiscOp : public Base
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{
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template <class InstType>
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MiscOp(InstType *inst, typename Base::ArgType idx) :
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Base(idx.index(), inst->dataSize)
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{}
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void
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print(std::ostream &os) const
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{
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X86StaticInst::printReg(os, RegId(MiscRegClass, this->index()),
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this->size);
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}
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};
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using FoldedDestOp = FoldedOp<DestOp>;
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using DbgDestOp = DbgOp<DestOp>;
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using CrDestOp = CrOp<DestOp>;
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using SegDestOp = SegOp<DestOp>;
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using MiscDestOp = MiscOp<DestOp>;
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using FoldedSrc1Op = FoldedOp<Src1Op>;
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using DbgSrc1Op = DbgOp<Src1Op>;
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using CrSrc1Op = CrOp<Src1Op>;
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using SegSrc1Op = SegOp<Src1Op>;
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using MiscSrc1Op = MiscOp<Src1Op>;
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using FoldedSrc2Op = FoldedOp<Src2Op>;
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struct Imm8Op
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{
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using ArgType = uint8_t;
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uint8_t imm8;
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template <class InstType>
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Imm8Op(InstType *inst, ArgType _imm8) : imm8(_imm8) {}
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void
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print(std::ostream &os) const
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{
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ccprintf(os, "%#x", imm8);
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}
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};
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template <typename Base, typename ...Operands>
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class InstOperands : public Base, public Operands...
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{
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protected:
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template <typename ...CTorArgs>
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InstOperands(ExtMachInst mach_inst, const char *mnem,
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const char *inst_mnem, uint64_t set_flags, OpClass op_class,
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typename Operands::ArgType... args, CTorArgs... ctor_args) :
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Base(mach_inst, mnem, inst_mnem, set_flags, op_class, ctor_args...),
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Operands(this, args)...
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{}
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std::string
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generateDisassembly(Addr pc,
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const Loader::SymbolTable *symtab) const override
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{
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std::stringstream response;
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Base::printMnemonic(response, this->instMnem, this->mnemonic);
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int count = 0;
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M5_FOR_EACH_IN_PACK(ccprintf(response, count++ ? ", " : ""),
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Operands::print(response));
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return response.str();
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}
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};
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}
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#endif //__ARCH_X86_INSTS_MICROOP_ARGS_HH__
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@@ -39,150 +39,19 @@
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#define __ARCH_X86_INSTS_MICROREGOP_HH__
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#include "arch/x86/insts/microop.hh"
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#include "arch/x86/insts/microop_args.hh"
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namespace X86ISA
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{
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struct DestOp
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{
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using ArgType = InstRegIndex;
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const RegIndex dest;
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const size_t size;
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RegIndex index() const { return dest; }
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DestOp(RegIndex _dest, size_t _size) : dest(_dest), size(_size) {}
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};
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struct Src1Op
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{
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using ArgType = InstRegIndex;
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const RegIndex src1;
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const size_t size;
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RegIndex index() const { return src1; }
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Src1Op(RegIndex _src1, size_t _size) : src1(_src1), size(_size) {}
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};
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struct Src2Op
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{
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using ArgType = InstRegIndex;
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const RegIndex src2;
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const size_t size;
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RegIndex index() const { return src2; }
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Src2Op(RegIndex _src2, size_t _size) : src2(_src2), size(_size) {}
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};
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template <class Base>
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struct FoldedOp : public Base
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{
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template <class InstType>
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FoldedOp(InstType *inst, typename Base::ArgType idx) :
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Base(INTREG_FOLDED(idx.index(), inst->foldOBit), inst->dataSize)
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{}
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void
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print(std::ostream &os) const
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{
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X86StaticInst::printReg(os, RegId(IntRegClass, this->index()),
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this->size);
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}
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};
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template <class Base>
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struct CrOp : public Base
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{
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template <class InstType>
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CrOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(), 0) {}
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void
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print(std::ostream &os) const
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{
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ccprintf(os, "cr%d", this->index());
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}
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};
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template <class Base>
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struct DbgOp : public Base
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{
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template <class InstType>
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DbgOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(), 0) {}
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void
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print(std::ostream &os) const
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{
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ccprintf(os, "dr%d", this->index());
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}
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};
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template <class Base>
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struct SegOp : public Base
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{
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template <class InstType>
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SegOp(InstType *inst, typename Base::ArgType idx) : Base(idx.index(), 0) {}
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void
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print(std::ostream &os) const
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{
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X86StaticInst::printSegment(os, this->index());
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}
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};
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template <class Base>
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struct MiscOp : public Base
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{
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template <class InstType>
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MiscOp(InstType *inst, typename Base::ArgType idx) :
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Base(idx.index(), inst->dataSize)
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{}
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void
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print(std::ostream &os) const
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{
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X86StaticInst::printReg(os, RegId(MiscRegClass, this->index()),
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this->size);
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}
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};
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using RegOpDest = FoldedOp<DestOp>;
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using RegOpDbgDest = DbgOp<DestOp>;
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using RegOpCrDest = CrOp<DestOp>;
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using RegOpSegDest = SegOp<DestOp>;
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using RegOpMiscDest = MiscOp<DestOp>;
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using RegOpSrc1 = FoldedOp<Src1Op>;
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using RegOpDbgSrc1 = DbgOp<Src1Op>;
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using RegOpCrSrc1 = CrOp<Src1Op>;
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using RegOpSegSrc1 = SegOp<Src1Op>;
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using RegOpMiscSrc1 = MiscOp<Src1Op>;
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using RegOpSrc2 = FoldedOp<Src2Op>;
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struct RegOpImm8
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{
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using ArgType = uint8_t;
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uint8_t imm8;
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template <class InstType>
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RegOpImm8(InstType *inst, ArgType _imm8) : imm8(_imm8) {}
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void
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print(std::ostream &os) const
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{
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ccprintf(os, "%#x", imm8);
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}
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};
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class RegOpBase : public X86MicroopBase
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{
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protected:
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const uint16_t ext;
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RegOpBase(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem,
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uint64_t set_flags, uint8_t data_size, uint16_t _ext,
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OpClass op_class) :
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uint64_t set_flags, OpClass op_class, uint8_t data_size,
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uint16_t _ext) :
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X86MicroopBase(mach_inst, mnem, inst_mnem, set_flags, op_class),
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ext(_ext), dataSize(data_size),
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foldOBit((data_size == 1 && !mach_inst.rex.present) ? 1 << 6 : 0)
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@@ -199,28 +68,7 @@ class RegOpBase : public X86MicroopBase
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};
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template <typename ...Operands>
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class RegOpT : public RegOpBase, public Operands...
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{
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protected:
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RegOpT(ExtMachInst mach_inst, const char *mnem, const char *inst_mnem,
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uint64_t set_flags, uint8_t data_size, uint16_t _ext,
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OpClass op_class, typename Operands::ArgType... args) :
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RegOpBase(mach_inst, mnem, inst_mnem, set_flags, data_size, _ext,
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op_class), Operands(this, args)...
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{}
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std::string
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generateDisassembly(Addr pc,
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const Loader::SymbolTable *symtab) const override
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{
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std::stringstream response;
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printMnemonic(response, instMnem, mnemonic);
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int count = 0;
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M5_FOR_EACH_IN_PACK(ccprintf(response, count++ ? ", " : ""),
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Operands::print(response));
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return response.str();
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}
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};
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using RegOpT = InstOperands<RegOpBase, Operands...>;
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}
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@@ -79,7 +79,7 @@ def template MicroRegOpDeclare {{
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uint64_t set_flags, uint8_t data_size, uint16_t _ext,
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Args... args) :
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%(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
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data_size, _ext, %(op_class)s, args...)
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%(op_class)s, args..., data_size, _ext)
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{
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%(set_reg_idx_arr)s;
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%(constructor)s;
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@@ -102,7 +102,7 @@ def template MicroRegOpBranchDeclare {{
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uint64_t set_flags, uint8_t data_size, uint16_t _ext,
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Args... args) :
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%(base_class)s(mach_inst, "%(mnemonic)s", inst_mnem, set_flags,
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data_size, _ext, %(op_class)s, args...)
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%(op_class)s, args..., data_size, _ext)
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{
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%(set_reg_idx_arr)s;
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%(constructor)s;
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@@ -213,20 +213,20 @@ let {{
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MicroRegOpExecute)
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dest_op = 'X86ISA::RegOpDest'
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dbg_dest_op = 'X86ISA::RegOpDbgDest'
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cr_dest_op = 'X86ISA::RegOpCrDest'
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seg_dest_op = 'X86ISA::RegOpSegDest'
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misc_dest_op = 'X86ISA::RegOpMiscDest'
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dest_op = 'X86ISA::FoldedDestOp'
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dbg_dest_op = 'X86ISA::DbgDestOp'
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cr_dest_op = 'X86ISA::CrDestOp'
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seg_dest_op = 'X86ISA::SegDestOp'
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misc_dest_op = 'X86ISA::MiscDestOp'
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src1_op = 'X86ISA::RegOpSrc1'
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dbg_src1_op = 'X86ISA::RegOpDbgSrc1'
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cr_src1_op = 'X86ISA::RegOpCrSrc1'
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seg_src1_op = 'X86ISA::RegOpSegSrc1'
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misc_src1_op = 'X86ISA::RegOpMiscSrc1'
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src1_op = 'X86ISA::FoldedSrc1Op'
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dbg_src1_op = 'X86ISA::DbgSrc1Op'
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cr_src1_op = 'X86ISA::CrSrc1Op'
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seg_src1_op = 'X86ISA::SegSrc1Op'
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misc_src1_op = 'X86ISA::MiscSrc1Op'
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src2_op = 'X86ISA::RegOpSrc2'
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imm_op = 'X86ISA::RegOpImm8'
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src2_op = 'X86ISA::FoldedSrc2Op'
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imm_op = 'X86ISA::Imm8Op'
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class RegOpMeta(type):
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def buildCppClasses(self, name, Name, suffix, code, big_code, \
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@@ -1489,7 +1489,7 @@ let {{
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super(SegOp, self).__init__(dest, src1, flags=flags,
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dataSize=dataSize)
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class WrSegOp(CondRegOp):
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class WrSegOp(SegOp):
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abstract = True
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operands = (seg_dest_op, src1_op)
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@@ -1513,7 +1513,7 @@ let {{
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SegAttrDest = psrc1;
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'''
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class RdSegOp(CondRegOp):
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class RdSegOp(SegOp):
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abstract = True
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operands = (dest_op, seg_src1_op)
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