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cpu: Style fixes in cpu/exec_context.hh and thread_context.hh.

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Change-Id: I2eb82cc6f6ba29c1df74e53b78b57c1a65577837
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39659
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-01-24 22:15:06 -08:00
parent ce20b07351
commit 92489797d4
2 changed files with 30 additions and 34 deletions
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11
src/cpu/thread_context.hh
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@@ -94,10 +94,7 @@ class ThreadContext : public PCEventScope
bool getUseForClone() { return useForClone; }
void setUseForClone(bool newUseForClone)
{
useForClone = newUseForClone;
}
void setUseForClone(bool new_val) { useForClone = new_val; }
enum Status
{
@@ -288,7 +285,7 @@ class ThreadContext : public PCEventScope
virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
virtual RegId flattenRegId(const RegId& regId) const = 0;
virtual RegId flattenRegId(const RegId& reg_id) const = 0;
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
@@ -332,8 +329,8 @@ class ThreadContext : public PCEventScope
const TheISA::VecRegContainer& val) = 0;
virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx,
const ElemIndex& elemIdx) const = 0;
virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
const ElemIndex& elem_idx) const = 0;
virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx,
const TheISA::VecElem& val) = 0;
virtual const TheISA::VecPredRegContainer &