Update functional memory to have a response event

Clean out old memory python files, move them into old_mem directory.  Maybe we should just delete them, they are under revision control.

Add new py files for new objects.

SConscript:
    Update because memory is just a header file now
base/chunk_generator.hh:
    Make Chunk Generator return the entire size if the chunk_size is set to zero.  Useful when trying to chunck on blocksize of memory, which can write large pieces of data.
cpu/simple/cpu.cc:
    Make sure to delete the pkt.
mem/physical.cc:
mem/physical.hh:
    Set up response event.
mem/port.cc:
    Rename rqst to req to conform to same standard naming convention.
python/m5/objects/PhysicalMemory.py:
    Update the params, inheritence

--HG--
extra : convert_revision : 857154ec256522baf423b715833930497999549b

SConscript

@@ -91,7 +91,6 @@ base_sources = Split('''
 	cpu/static_inst.cc
         cpu/sampler/sampler.cc
 
-        mem/memory.cc
         mem/page_table.cc
         mem/physical.cc
         mem/port.cc

base/chunk_generator.hh

@@ -82,11 +82,18 @@ class ChunkGenerator
         // set up initial chunk.
         curAddr = startAddr;
 
-        // nextAddr should be *next* chunk start
-        nextAddr = roundUp(startAddr, chunkSize);
-        if (curAddr == nextAddr) {
-            // ... even if startAddr is already chunk-aligned
-            nextAddr += chunkSize;
+        if (chunkSize == 0) //Special Case, if we see 0, assume no chuncking
+        {
+            nextAddr = startAddr + totalSize;
+        }
+        else
+        {
+            // nextAddr should be *next* chunk start
+            nextAddr = roundUp(startAddr, chunkSize);
+            if (curAddr == nextAddr) {
+                // ... even if startAddr is already chunk-aligned
+                nextAddr += chunkSize;
+            }
         }
 
         // how many bytes are left between curAddr and the end of this chunk?

cpu/simple/cpu.cc

@@ -674,6 +674,8 @@ SimpleCPU::sendIcacheRequest()
     icacheStallCycles += latency;
 
     _status = IcacheAccessComplete;
+
+    delete pkt;
 #endif
 }
 

mem/physical.cc

@@ -46,11 +46,31 @@
 #include "mem/physical.hh"
 #include "sim/host.hh"
 #include "sim/builder.hh"
+#include "sim/eventq.hh"
 #include "targetarch/isa_traits.hh"
 
 
 using namespace std;
 
+PhysicalMemory::MemResponseEvent::MemResponseEvent(Packet &pkt, MemoryPort* _m)
+    : Event(&mainEventQueue, CPU_Tick_Pri), pkt(pkt), memoryPort(_m)
+{
+
+    this->setFlags(AutoDelete);
+}
+
+void
+PhysicalMemory::MemResponseEvent::process()
+{
+    memoryPort->sendTiming(pkt);
+}
+
+const char *
+PhysicalMemory::MemResponseEvent::description()
+{
+    return "Physical Memory Timing Access respnse event";
+}
+
 #if FULL_SYSTEM
 PhysicalMemory::PhysicalMemory(const string &n, Range<Addr> range,
                                MemoryController *mmu, const std::string &fname)
@@ -157,7 +177,10 @@ bool
 PhysicalMemory::doTimingAccess (Packet &pkt)
 {
     doFunctionalAccess(pkt);
-    //Schedule a response event at curTick + lat;
+
+    MemResponseEvent* response = new MemResponseEvent(pkt, &memoryPort);
+    response->schedule(curTick + lat);
+
     return true;
 }
 
@@ -213,6 +236,11 @@ PhysicalMemory::MemoryPort::getDeviceAddressRanges(AddrRangeList &range_list,
     panic("??");
 }
 
+int
+PhysicalMemory::MemoryPort::deviceBlockSize()
+{
+    return memory->deviceBlockSize();
+}
 
 bool
 PhysicalMemory::MemoryPort::recvTiming(Packet &pkt)

mem/physical.hh

@@ -35,6 +35,8 @@
 #include "base/range.hh"
 #include "mem/memory.hh"
 #include "mem/packet.hh"
+#include "mem/port.hh"
+#include "sim/eventq.hh"
 
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
@@ -63,7 +65,6 @@ class PhysicalMemory : public Memory
                                             bool &owner);
 
         virtual int deviceBlockSize();
-
     };
 
     MemoryPort memoryPort;
@@ -72,7 +73,15 @@ class PhysicalMemory : public Memory
 
     int lat;
 
-    //event to send response needs to be here
+    struct MemResponseEvent : public Event
+    {
+        Packet pkt;
+        MemoryPort *memoryPort;
+
+        MemResponseEvent(Packet &pkt, MemoryPort *memoryPort);
+        void process();
+        const char *description();
+    };
 
   private:
     // prevent copying of a MainMemory object
@@ -98,7 +107,7 @@ class PhysicalMemory : public Memory
     void prot_access_error(Addr addr, int size, Command func);
 
   public:
-    virtual int deviceBlockSize();
+    int deviceBlockSize();
 
     void prot_memset(Addr addr, uint8_t val, int size);
 

mem/port.cc

@@ -36,15 +36,15 @@
 void
 Port::blobHelper(Addr addr, uint8_t *p, int size, Command cmd)
 {
-    Request rqst;
+    Request req;
     Packet pkt;
-    pkt.req = &rqst;
+    pkt.req = &req;
     pkt.cmd = cmd;
 
     for (ChunkGenerator gen(addr, size, peerBlockSize());
          !gen.done(); gen.next()) {
-        pkt.addr = rqst.paddr = gen.addr();
-        pkt.size = rqst.size = gen.size();
+        pkt.addr = req.paddr = gen.addr();
+        pkt.size = req.size = gen.size();
         pkt.data = p;
         sendFunctional(pkt);
         p += gen.size();

python/m5/objects/MemObject.py

@@ -0,0 +1,5 @@
+from m5 import *
+
+class MemObject(SimObject):
+    type = 'MemObject'
+    abstract = True

python/m5/objects/PhysicalMemory.py

@@ -1,7 +1,7 @@
 from m5 import *
-from FunctionalMemory import FunctionalMemory
+from Memory import Memory
 
-class PhysicalMemory(FunctionalMemory):
+class PhysicalMemory(Memory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")