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arch-arm: default MIDR for Armv8 ISA processors

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Software such as Trusted Firmware-A checks the MIDR register
to identify which core model is present in the platform.
The previous default value referred to a Cortex-A15 Armv7-A
processor, however when AArch64 is enabled, an Armv8 processor
is expected.
This patch assigns the Cortex-A57 MIDR if AArch64 is enabled.

Change-Id: Id1677a77d2f04843423f7b013405445f3d253399
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22846
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Adrian Herrera
2019-10-16 10:04:01 +01:00
committed by Giacomo Travaglini
parent 0793149cbb
commit 8e8214da55
2 changed files with 19 additions and 4 deletions
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6
src/arch/arm/ArmISA.py
View File

@@ -57,7 +57,11 @@ class ArmISA(SimObject):
pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
midr = Param.UInt32(0x410fc0f0, "MIDR value")
# If no MIDR value is provided, 0x0 is treated by gem5 as follows:
# When 'highest_el_is_64' (AArch64 support) is:
# True -> Cortex-A57 TRM r0p0 MIDR is used
# False -> Cortex-A15 TRM r0p0 MIDR is used
midr = Param.UInt32(0x0, "MIDR value")
# See section B4.1.89 - B4.1.92 of the ARM ARM
# VMSAv7 support

17
src/arch/arm/isa.cc
View File

@@ -319,9 +319,20 @@ void
ISA::initID32(const ArmISAParams *p)
{
// Initialize configurable default values
miscRegs[MISCREG_MIDR] = p->midr;
miscRegs[MISCREG_MIDR_EL1] = p->midr;
miscRegs[MISCREG_VPIDR] = p->midr;
uint32_t midr;
if (p->midr != 0x0)
midr = p->midr;
else if (highestELIs64)
// Cortex-A57 TRM r0p0 MIDR
midr = 0x410fd070;
else
// Cortex-A15 TRM r0p0 MIDR
midr = 0x410fc0f0;
miscRegs[MISCREG_MIDR] = midr;
miscRegs[MISCREG_MIDR_EL1] = midr;
miscRegs[MISCREG_VPIDR] = midr;
miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;