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arch-arm: Add missing fall-through defaults

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Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Javier Setoain
2019-03-14 18:06:05 +00:00
committed by Giacomo Travaglini
parent f838a332be
commit 8e1a141818
2 changed files with 9 additions and 0 deletions
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4
src/arch/arm/isa/formats/sve_2nd_level.isa
View File

@@ -118,6 +118,7 @@ namespace Aarch64
return new Unknown64(machInst);
}
}
break;
}
case 0x3:
{
@@ -532,6 +533,7 @@ namespace Aarch64
return new SveIndexII<int64_t>(machInst,
zd, imm5, imm5b);
}
break;
}
case 1:
{ // INDEX (scalar, immediate)
@@ -552,6 +554,7 @@ namespace Aarch64
return new SveIndexRI<int64_t>(machInst,
zd, zn, imm5);
}
break;
}
case 2:
{ // INDEX (immediate, scalar)
@@ -572,6 +575,7 @@ namespace Aarch64
return new SveIndexIR<int64_t>(machInst,
zd, imm5, zm);
}
break;
}
case 3:
{ // INDEX (scalars)

5
src/arch/arm/isa/formats/sve_top_level.isa
View File

@@ -128,6 +128,7 @@ namespace Aarch64
return decodeSveIntArithUnaryPred(machInst);
}
}
break;
}
case 0x1:
{
@@ -166,6 +167,7 @@ namespace Aarch64
case 0x3:
return decodeSveElemCount(machInst);
}
break;
}
case 0x2:
if (bits(machInst, 20)) {
@@ -195,6 +197,7 @@ namespace Aarch64
case 0x3:
return decodeSveSelVec(machInst);
}
break;
}
case 0x4:
return decodeSveIntCmpVec(machInst);
@@ -279,6 +282,7 @@ namespace Aarch64
case 0x3:
return decodeSveFpAccumReduc(machInst);
}
break;
}
case 0x2:
return decodeSveFpArithPred(machInst);
@@ -286,6 +290,7 @@ namespace Aarch64
return decodeSveFpUnaryPred(machInst);
}
}
break;
}
case 0x3:
return decodeSveFpFusedMulAdd(machInst);