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arch-arm: Fix masking in CPACR_EL1

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Some bits in CPACR_EL1 are RES0 but not RAZ/WI. For instance, bit
CPACR_EL1[31] is RES0 but should be made stateful, since it allows
programing of CPACR.ASEDIS. Therefore the masking of CPACR_EL1
is removed.

Change-Id: If1fa3fa1e06bc38495b8afce2c635f3ddf76ce32
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10046
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Chuan Zhu
2018-01-17 10:59:30 +00:00
committed by Giacomo Travaglini
parent abbe32b6ac
commit 8dabce896a
1 changed files with 0 additions and 11 deletions
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11
src/arch/arm/isa.cc
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@@ -754,17 +754,6 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
miscRegName[misc_reg], newVal);
}
break;
case MISCREG_CPACR_EL1:
{
const uint32_t ones = (uint32_t)(-1);
CPACR cpacrMask = 0;
cpacrMask.tta = ones;
cpacrMask.fpen = ones;
newVal &= cpacrMask;
DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
miscRegName[misc_reg], newVal);
}
break;
case MISCREG_CPTR_EL2:
{
const uint32_t ones = (uint32_t)(-1);