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arm, dev: stub out GIC distributor interrupt groups

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We don't implement the GICD_IGROUPRn registers, which is allowed, but
to be correct, they should be RAZ/WI (read as zero, writes ignored).

Change-Id: I8039baf72f45c0095f41e165b8e327c79b1ac082
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2620
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Curtis Dunham
2017-03-29 14:07:03 -05:00
committed by Andreas Sandberg
parent c6a6fbe9fd
commit 8ced1bd0b0
2 changed files with 10 additions and 0 deletions
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9
src/dev/arm/gic_pl390.cc
View File

@@ -52,6 +52,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
const AddrRange Pl390::GICD_IGROUPR (0x080, 0x0ff);
const AddrRange Pl390::GICD_ISENABLER (0x100, 0x17f);
const AddrRange Pl390::GICD_ICENABLER (0x180, 0x1ff);
const AddrRange Pl390::GICD_ISPENDR (0x200, 0x27f);
@@ -153,6 +154,10 @@ Pl390::readDistributor(PacketPtr pkt)
uint32_t
Pl390::readDistributor(ContextID ctx, Addr daddr, size_t resp_sz)
{
if (GICD_IGROUPR.contains(daddr)) {
return 0; // unimplemented; RAZ (read as zero)
}
if (GICD_ISENABLER.contains(daddr)) {
uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
assert(ix < 32);
@@ -387,6 +392,10 @@ void
Pl390::writeDistributor(ContextID ctx, Addr daddr, uint32_t data,
size_t data_sz)
{
if (GICD_IGROUPR.contains(daddr)) {
return; // unimplemented; WI (writes ignored)
}
if (GICD_ISENABLER.contains(daddr)) {
uint32_t ix = (daddr - GICD_ISENABLER.start()) >> 2;
assert(ix < 32);

1
src/dev/arm/gic_pl390.hh
View File

@@ -71,6 +71,7 @@ class Pl390 : public BaseGic, public BaseGicRegisters
DIST_SIZE = 0xfff
};
static const AddrRange GICD_IGROUPR; // interrupt group (unimplemented)
static const AddrRange GICD_ISENABLER; // interrupt set enable
static const AddrRange GICD_ICENABLER; // interrupt clear enable
static const AddrRange GICD_ISPENDR; // set pending interrupt