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arm: Don't speculatively access most miscregisters.

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Speculative exeuction can cause panics in detailed execution mode that
shouldn't happen.
This commit is contained in:
Akash Bagdia
2014-09-02 11:26:32 +01:00
parent d6f1c6ce89
commit 8b7724d04c
2 changed files with 2 additions and 2 deletions
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2
src/arch/arm/isa/insts/misc.isa
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@@ -219,7 +219,7 @@ let {{
msrBankedRegIop = InstObjParams("msr", "MsrBankedReg", "MsrRegOp",
{ "code": msrBankedRegCode,
"predicate_test": predicateTest },
["IsSerializeAfter"])
["IsSerializeAfter", "IsNonSpeculative"])
header_output += MsrBankedRegDeclare.subst(msrBankedRegIop)
decoder_output += MsrBankedRegConstructor.subst(msrBankedRegIop)
exec_output += PredOpExecute.subst(msrBankedRegIop)

2
src/arch/arm/miscregs.cc
View File

@@ -758,7 +758,7 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = {
// MISCREG_CNTP_CVAL
bitset<NUM_MISCREG_INFOS>(string("0000000000000001001")),
// MISCREG_CNTP_CVAL_NS
bitset<NUM_MISCREG_INFOS>(string("1100110011111110000")),
bitset<NUM_MISCREG_INFOS>(string("1100110011111110001")),
// MISCREG_CNTP_CVAL_S
bitset<NUM_MISCREG_INFOS>(string("0011001100111110000")),
// MISCREG_CNTV_CVAL