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mem-ruby: Add missing CHI transition SD_RSC + *_Stale->BUSY_BLKD

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Related JIRA: https://gem5.atlassian.net/browse/GEM5-1180

Change-Id: Ife83bebcaa48345633fce0a0de08394e30c1a796
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56083
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Tiago Muck <tiago.muck@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabriel Busnot
2022-01-27 13:32:18 +01:00
committed by Meatboy 106
parent 7c0c23b2da
commit 8a7fcd340f
1 changed files with 1 additions and 1 deletions
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2
src/mem/ruby/protocol/chi/CHI-cache-transitions.sm
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@@ -498,7 +498,7 @@ transition({UD_RU, UC_RU, RU}, WriteEvictFull, BUSY_BLKD) {
ProcessNextState;
}
transition({UD_RSC, UC_RSC, SC_RSC, UD, RU, RSD, RUSD, RUSC, UD_RSD, SD_RSD, RSC, UD_RU, UC_RU, SD, UC, SC, I},
transition({UD_RSC, UC_RSC, SC_RSC, SD_RSC, UD, RU, RSD, RUSD, RUSC, UD_RSD, SD_RSD, RSC, UD_RU, UC_RU, SD, UC, SC, I},
{WriteBackFull_Stale, WriteEvictFull_Stale, WriteCleanFull_Stale}, BUSY_BLKD) {
Initiate_Request_Stale;
Initiate_CopyBack_Stale;