arch-arm: Add DVM ISA templates

These will be used by DVM instructions:

* TLBI Shareable
* DSB Shareable

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I32f83e08360ceb7ba324d07c72fe6addeb4bbbca
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56604
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa/templates/misc64.isa

@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2011,2017-2020 ARM Limited
+// Copyright (c) 2011,2017-2022 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -233,3 +233,102 @@ def template RegNoneConstructor {{
         %(constructor)s;
     }
 }};
+
+def template DvmTlbiDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+  private:
+    %(reg_idx_arr_decl)s;
+    const bool dvmEnabled;
+
+  public:
+    // Constructor
+    %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
+            IntRegIndex _op1, uint64_t _imm, bool dvm_enabled);
+
+    Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+    Fault completeAcc(PacketPtr, ExecContext *,
+                      Trace::InstRecord *) const override;
+    Fault execute(ExecContext *, Trace::InstRecord *) const override;
+};
+}};
+
+def template DvmDeclare {{
+    /**
+     * Static instruction class for "%(mnemonic)s".
+     */
+    class %(class_name)s : public %(base_class)s
+    {
+      private:
+        %(reg_idx_arr_decl)s;
+        const bool dvmEnabled;
+
+      public:
+        /// Constructor.
+        %(class_name)s(ExtMachInst machInst, bool dvm_enabled);
+        Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+        Fault completeAcc(PacketPtr, ExecContext *,
+                          Trace::InstRecord *) const override;
+        Fault execute(ExecContext *, Trace::InstRecord *) const override;
+    };
+}};
+
+def template DvmTlbiConstructor {{
+    %(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
+                                   IntRegIndex _op1, uint64_t _imm,
+                                   bool dvm_enabled) :
+        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                       _dest, _op1, _imm),
+        dvmEnabled(dvm_enabled)
+    {
+        %(set_reg_idx_arr)s;
+        %(constructor)s;
+
+        if (dvmEnabled) {
+            flags[IsLoad] = true;
+        }
+    }
+}};
+
+def template DvmConstructor {{
+    %(class_name)s::%(class_name)s(ExtMachInst machInst, bool dvm_enabled) :
+        %(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
+        dvmEnabled(dvm_enabled)
+    {
+        %(set_reg_idx_arr)s;
+        %(constructor)s;
+
+        if (dvmEnabled) {
+            flags[IsLoad] = true;
+        }
+    }
+}};
+
+def template DvmInitiateAcc {{
+    Fault
+    %(class_name)s::initiateAcc(ExecContext *xc,
+                                Trace::InstRecord *traceData) const
+    {
+        Fault fault = NoFault;
+
+        %(op_decl)s;
+        %(op_rd)s;
+        %(code)s;
+
+        %(dvm_code)s;
+
+        if (fault == NoFault) {
+            %(op_wb)s;
+        }
+        return fault;
+    }
+}};
+
+def template DvmCompleteAcc {{
+    Fault
+    %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
+                                Trace::InstRecord *traceData) const
+    {
+        return NoFault;
+    }
+}};