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cpu: Get rid of the (read|set)RegOtherThread methods.

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These are implemented by MIPS internally now.

Change-Id: If7465e1666e51e1314968efb56a5a814e62ee2d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18436
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2019-04-28 08:56:22 +00:00
parent a632ee72ad
commit 88fc141f72
6 changed files with 0 additions and 119 deletions
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15
src/cpu/checker/cpu.hh
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@@ -483,21 +483,6 @@ class CheckerCPU : public BaseCPU, public ExecContext
return this->setMiscReg(reg.index(), val);
}
#if THE_ISA == MIPS_ISA
RegVal
readRegOtherThread(const RegId &misc_reg, ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
return 0;
}
void
setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
{
panic("MIPS MT not defined for CheckerCPU.\n");
}
#endif
/////////////////////////////////////////
void

14
src/cpu/exec_context.hh
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@@ -353,20 +353,6 @@ class ExecContext {
virtual AddressMonitor *getAddrMonitor() = 0;
/** @} */
/**
* @{
* @name MIPS-Specific Interfaces
*/
#if THE_ISA == MIPS_ISA
virtual RegVal readRegOtherThread(const RegId &reg,
ThreadID tid=InvalidThreadID) = 0;
virtual void setRegOtherThread(const RegId& reg, RegVal val,
ThreadID tid=InvalidThreadID) = 0;
#endif
/** @} */
};
#endif // __CPU_EXEC_CONTEXT_HH__

45
src/cpu/minor/exec_context.hh
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@@ -441,51 +441,6 @@ class ExecContext : public ::ExecContext
BaseCPU *getCpuPtr() { return &cpu; }
/* MIPS: other thread register reading/writing */
RegVal
readRegOtherThread(const RegId &reg, ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
? &thread : cpu.threads[tid]);
switch (reg.classValue()) {
case IntRegClass:
return other_thread->readIntReg(reg.index());
break;
case FloatRegClass:
return other_thread->readFloatReg(reg.index());
break;
case MiscRegClass:
return other_thread->readMiscReg(reg.index());
default:
panic("Unexpected reg class! (%s)",
reg.className());
return 0;
}
}
void
setRegOtherThread(const RegId &reg, RegVal val,
ThreadID tid=InvalidThreadID)
{
SimpleThread *other_thread = (tid == InvalidThreadID
? &thread : cpu.threads[tid]);
switch (reg.classValue()) {
case IntRegClass:
return other_thread->setIntReg(reg.index(), val);
break;
case FloatRegClass:
return other_thread->setFloatReg(reg.index(), val);
break;
case MiscRegClass:
return other_thread->setMiscReg(reg.index(), val);
default:
panic("Unexpected reg class! (%s)",
reg.className());
}
}
public:
// monitor/mwait funtions
void armMonitor(Addr address) override

15
src/cpu/o3/dyn_inst.hh
View File

@@ -429,21 +429,6 @@ class BaseO3DynInst : public BaseDynInst<Impl>
this->cpu->setCCReg(this->_destRegIdx[idx], val);
BaseDynInst<Impl>::setCCRegOperand(si, idx, val);
}
#if THE_ISA == MIPS_ISA
RegVal
readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
{
panic("MIPS MT not defined for O3 CPU.\n");
return 0;
}
void
setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
{
panic("MIPS MT not defined for O3 CPU.\n");
}
#endif
};
#endif // __CPU_O3_ALPHA_DYN_INST_HH__

19
src/cpu/simple/exec_context.hh
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@@ -566,25 +566,6 @@ class SimpleExecContext : public ExecContext {
{
return cpu->getCpuAddrMonitor(thread->threadId());
}
#if THE_ISA == MIPS_ISA
RegVal
readRegOtherThread(const RegId& reg, ThreadID tid=InvalidThreadID)
override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
void
setRegOtherThread(const RegId& reg, RegVal val,
ThreadID tid=InvalidThreadID) override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
#endif
};
#endif // __CPU_EXEC_CONTEXT_HH__

11
src/cpu/thread_context.hh
View File

@@ -299,17 +299,6 @@ class ThreadContext
virtual RegId flattenRegId(const RegId& regId) const = 0;
virtual RegVal
readRegOtherThread(const RegId& misc_reg, ThreadID tid)
{
return 0;
}
virtual void
setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
{
}
// Also not necessarily the best location for these two. Hopefully will go
// away once we decide upon where st cond failures goes.
virtual unsigned readStCondFailures() const = 0;