arch: Move setting up RegClassInfos into the arches.

Also remove no longer global constants from arch/registers.hh if they
are no longer used locally.

Change-Id: I1d1589db3dd4c51a5ec11e32348d394261e36d17
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41734
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/freebsd/se_workload.hh

@@ -34,8 +34,8 @@
 #ifndef __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
 #define __ARCH_ARM_FREEBSD_SE_WORKLOAD_HH__
 
+#include "arch/arm/ccregs.hh"
 #include "arch/arm/freebsd/freebsd.hh"
-#include "arch/arm/registers.hh"
 #include "arch/arm/se_workload.hh"
 #include "params/ArmEmuFreebsd.hh"
 #include "sim/syscall_desc.hh"

src/arch/arm/htm.cc

@@ -36,6 +36,9 @@
  */
 
 #include "arch/arm/htm.hh"
+
+#include "arch/arm/intregs.hh"
+#include "arch/arm/miscregs.hh"
 #include "cpu/thread_context.hh"
 
 void
@@ -70,7 +73,7 @@ ArmISA::HTMCheckpoint::save(ThreadContext *tc)
     //tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
     nzcv = tc->readMiscReg(MISCREG_NZCV);
     daif = tc->readMiscReg(MISCREG_DAIF);
-    for (auto n = 0; n < NumIntArchRegs; n++) {
+    for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
         x[n] = tc->readIntReg(n);
     }
     // TODO first detect if FP is enabled at this EL
@@ -97,7 +100,7 @@ ArmISA::HTMCheckpoint::restore(ThreadContext *tc, HtmFailureFaultCause cause)
     //tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
     tc->setMiscReg(MISCREG_NZCV, nzcv);
     tc->setMiscReg(MISCREG_DAIF, daif);
-    for (auto n = 0; n < NumIntArchRegs; n++) {
+    for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
         tc->setIntReg(n, x[n]);
     }
     // TODO first detect if FP is enabled at this EL

src/arch/arm/htm.hh

@@ -44,6 +44,7 @@
  * ISA-specific types for hardware transactional memory.
  */
 
+#include "arch/arm/intregs.hh"
 #include "arch/arm/registers.hh"
 #include "arch/generic/htm.hh"
 #include "base/types.hh"
@@ -70,7 +71,7 @@ class HTMCheckpoint : public BaseHTMCheckpoint
   private:
     uint8_t rt; // TSTART destination register
     Addr nPc; // Fallback instruction address
-    std::array<RegVal, NumIntArchRegs> x; // General purpose registers
+    std::array<RegVal, NUM_ARCH_INTREGS> x; // General purpose registers
     std::array<VecRegContainer, NumVecRegs> z; // Vector registers
     std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
     Addr sp; // Stack Pointer at current EL

src/arch/arm/isa.cc

@@ -47,6 +47,7 @@
 #include "arch/arm/tlbi_op.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
+#include "cpu/reg_class.hh"
 #include "debug/Arm.hh"
 #include "debug/MiscRegs.hh"
 #include "dev/arm/generic_timer.hh"
@@ -65,6 +66,16 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
     pmu(p.pmu), impdefAsNop(p.impdef_nop),
     afterStartup(false)
 {
+    _regClasses.insert(_regClasses.end(), {
+            { NUM_INTREGS },
+            { 0 },
+            { NumVecRegs },
+            { NumVecRegs * TheISA::NumVecElemPerVecReg },
+            { NumVecPredRegs },
+            { NUM_CCREGS },
+            { NUM_MISCREGS }
+    });
+
     miscRegs[MISCREG_SCTLR_RST] = 0;
 
     // Hook up a dummy device if we haven't been configured with a
@@ -484,7 +495,7 @@ ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
 RegVal
 ISA::readMiscRegNoEffect(int misc_reg) const
 {
-    assert(misc_reg < NumMiscRegs);
+    assert(misc_reg < NUM_MISCREGS);
 
     const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
     const auto &map = getMiscIndices(misc_reg);
@@ -810,7 +821,7 @@ ISA::readMiscReg(int misc_reg)
 void
 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
 {
-    assert(misc_reg < NumMiscRegs);
+    assert(misc_reg < NUM_MISCREGS);
 
     const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
     const auto &map = getMiscIndices(misc_reg);

src/arch/arm/isa.hh

@@ -454,7 +454,7 @@ namespace ArmISA
 
         void initializeMiscRegMetadata();
 
-        RegVal miscRegs[NumMiscRegs];
+        RegVal miscRegs[NUM_MISCREGS];
         const IntRegIndex *intRegMap;
 
         void

src/arch/arm/isa_device.cc

@@ -37,6 +37,7 @@
 
 #include "arch/arm/isa_device.hh"
 
+#include "arch/arm/miscregs.hh"
 #include "base/logging.hh"
 
 namespace ArmISA

src/arch/arm/nativetrace.cc

@@ -40,6 +40,7 @@
 
 #include "arch/arm/nativetrace.hh"
 
+#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/miscregs.hh"
 #include "cpu/thread_context.hh"

src/arch/arm/process.cc

@@ -40,7 +40,9 @@
 
 #include "arch/arm/process.hh"
 
+#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
+#include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "base/loader/elf_object.hh"
 #include "base/loader/object_file.hh"

src/arch/arm/registers.hh

@@ -41,10 +41,7 @@
 #ifndef __ARCH_ARM_REGISTERS_HH__
 #define __ARCH_ARM_REGISTERS_HH__
 
-#include "arch/arm/ccregs.hh"
 #include "arch/arm/intregs.hh"
-#include "arch/arm/miscregs.hh"
-#include "arch/arm/types.hh"
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
 
@@ -68,14 +65,6 @@ using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
                                       VecPredRegHasPackedRepr, true>;
 using VecPredRegContainer = VecPredReg::Container;
 
-// Constants Related to the number of registers
-// Int, Float, CC, Misc
-const int NumIntArchRegs = NUM_ARCH_INTREGS;
-const int NumIntRegs = NUM_INTREGS;
-const int NumFloatRegs = 0; // Float values are stored in the VecRegs
-const int NumCCRegs = NUM_CCREGS;
-const int NumMiscRegs = NUM_MISCREGS;
-
 // Vec, PredVec
 // NumFloatV7ArchRegs: This in theory should be 32.
 // However in A32 gem5 is splitting double register accesses in two
@@ -89,9 +78,6 @@ const int NumVecIntrlvRegs = 4;
 const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;
 const int NumVecPredRegs = 18;  // P0-P15, FFR, UREG0
 
-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
-    NumVecPredRegs + NumMiscRegs;
-
 // Semantically meaningful register indices
 const int ReturnValueReg = 0;
 const int ReturnValueReg1 = 1;

src/arch/arm/tracers/tarmac_base.cc

@@ -40,7 +40,7 @@
 #include <algorithm>
 #include <string>
 
-#include "config/the_isa.hh"
+#include "arch/arm/miscregs.hh"
 #include "cpu/reg_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"

src/arch/arm/tracers/tarmac_record.hh

@@ -45,6 +45,7 @@
 
 #include <memory>
 
+#include "arch/arm/miscregs.hh"
 #include "arch/arm/tracers/tarmac_base.hh"
 #include "base/printable.hh"
 #include "config/the_isa.hh"

src/arch/arm/utility.cc

@@ -39,8 +39,10 @@
 
 #include <memory>
 
+#include "arch/arm/ccregs.hh"
 #include "arch/arm/faults.hh"
 #include "arch/arm/interrupts.hh"
+#include "arch/arm/intregs.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/mmu.hh"
 #include "arch/arm/system.hh"
@@ -74,16 +76,13 @@ copyVecRegs(ThreadContext *src, ThreadContext *dest)
 void
 copyRegs(ThreadContext *src, ThreadContext *dest)
 {
-    for (int i = 0; i < NumIntRegs; i++)
+    for (int i = 0; i < NUM_INTREGS; i++)
         dest->setIntRegFlat(i, src->readIntRegFlat(i));
 
-    for (int i = 0; i < NumFloatRegs; i++)
-        dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
-
-    for (int i = 0; i < NumCCRegs; i++)
+    for (int i = 0; i < NUM_CCREGS; i++)
         dest->setCCReg(i, src->readCCReg(i));
 
-    for (int i = 0; i < NumMiscRegs; i++)
+    for (int i = 0; i < NUM_MISCREGS; i++)
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 
     copyVecRegs(src, dest);

src/arch/arm/utility.hh

@@ -42,6 +42,7 @@
 #ifndef __ARCH_ARM_UTILITY_HH__
 #define __ARCH_ARM_UTILITY_HH__
 
+#include "arch/arm/ccregs.hh"
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"

src/arch/generic/isa.hh

@@ -42,7 +42,6 @@
 
 #include <vector>
 
-#include "arch/registers.hh"
 #include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"
 
@@ -58,17 +57,7 @@ class BaseISA : public SimObject
 
     ThreadContext *tc = nullptr;
 
-    RegClasses _regClasses = {
-#if THE_ISA != NULL_ISA
-        { TheISA::NumIntRegs },
-        { TheISA::NumFloatRegs },
-        { TheISA::NumVecRegs },
-        { TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg },
-        { TheISA::NumVecPredRegs },
-        { TheISA::NumCCRegs },
-        { TheISA::NumMiscRegs }
-#endif // THE_ISA != NULL_ISA
-    };
+    RegClasses _regClasses;
 
   public:
     virtual void takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc) {}

src/arch/mips/isa.cc

@@ -33,6 +33,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/bitfield.hh"
 #include "cpu/base.hh"
+#include "cpu/reg_class.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
 #include "params/MipsISA.hh"
@@ -41,7 +42,7 @@ namespace MipsISA
 {
 
 std::string
-ISA::miscRegNames[NumMiscRegs] =
+ISA::miscRegNames[MISCREG_NUMREGS] =
 {
     "Index", "MVPControl", "MVPConf0", "MVPConf1", "", "", "", "",
     "Random", "VPEControl", "VPEConf0", "VPEConf1",
@@ -90,17 +91,27 @@ ISA::miscRegNames[NumMiscRegs] =
 ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
     numVpes(p.num_vpes)
 {
-    miscRegFile.resize(NumMiscRegs);
-    bankType.resize(NumMiscRegs);
+    _regClasses.insert(_regClasses.end(), {
+            { NumIntRegs },
+            { NumFloatRegs },
+            { 1 }, // Not applicable to MIPS.
+            { 2 }, // Not applicable to MIPS.
+            { 1 }, // Not applicable to MIPS.
+            { 0 }, // Not applicable to MIPS.
+            { MISCREG_NUMREGS }
+    });
 
-    for (int i=0; i < NumMiscRegs; i++) {
+    miscRegFile.resize(MISCREG_NUMREGS);
+    bankType.resize(MISCREG_NUMREGS);
+
+    for (int i = 0; i < MISCREG_NUMREGS; i++) {
         miscRegFile[i].resize(1);
         bankType[i] = perProcessor;
     }
 
-    miscRegFile_WriteMask.resize(NumMiscRegs);
+    miscRegFile_WriteMask.resize(MISCREG_NUMREGS);
 
-    for (int i = 0; i < NumMiscRegs; i++) {
+    for (int i = 0; i < MISCREG_NUMREGS; i++) {
         miscRegFile_WriteMask[i].push_back(0);
     }
 
@@ -143,7 +154,7 @@ ISA::ISA(const Params &p) : BaseISA(p), numThreads(p.num_threads),
 void
 ISA::clear()
 {
-    for (int i = 0; i < NumMiscRegs; i++) {
+    for (int i = 0; i < MISCREG_NUMREGS; i++) {
         for (int j = 0; j < miscRegFile[i].size(); j++)
             miscRegFile[i][j] = 0;
 

src/arch/mips/isa.hh

@@ -125,7 +125,7 @@ namespace MipsISA
         // and if necessary alert the CPU
         void updateCPU(BaseCPU *cpu);
 
-        static std::string miscRegNames[NumMiscRegs];
+        static std::string miscRegNames[MISCREG_NUMREGS];
 
       public:
         ISA(const Params &p);

src/arch/mips/registers.hh

@@ -49,11 +49,6 @@ const int NumFloatSpecialRegs = 5;
 const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
-const int NumVecRegs = 1;  // Not applicable to MIPS
-                           // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to MIPS
-                               // (1 to prevent warnings)
-const int NumCCRegs = 0;
 
 const uint32_t MIPS32_QNAN = 0x7fbfffff;
 const uint64_t MIPS64_QNAN = 0x7ff7ffffffffffffULL;
@@ -266,8 +261,6 @@ enum MiscRegIndex{
     MISCREG_NUMREGS
 };
 
-const int NumMiscRegs = MISCREG_NUMREGS;
-
 // Not applicable to MIPS
 using VecElem = ::DummyVecElem;
 using VecReg = ::DummyVecReg;

src/arch/mips/utility.cc

@@ -216,11 +216,8 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     for (int i = 0; i < NumFloatRegs; i++)
         dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
 
-    // Would need to add condition-code regs if implemented
-    assert(NumCCRegs == 0);
-
     // Copy misc. registers
-    for (int i = 0; i < NumMiscRegs; i++)
+    for (int i = 0; i < MISCREG_NUMREGS; i++)
         dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
 
     // Copy over the PC State

src/arch/power/isa.cc

@@ -37,6 +37,8 @@
 
 #include "arch/power/isa.hh"
 
+#include "arch/power/miscregs.hh"
+#include "arch/power/registers.hh"
 #include "params/PowerISA.hh"
 
 namespace PowerISA
@@ -44,6 +46,15 @@ namespace PowerISA
 
 ISA::ISA(const Params &p) : BaseISA(p)
 {
+    _regClasses.insert(_regClasses.end(), {
+            { NumIntRegs },
+            { NumFloatRegs },
+            { 1 },
+            { 2 },
+            { 1 },
+            { 0 },
+            { NUM_MISCREGS }
+    });
     clear();
 }
 

src/arch/power/isa.hh

@@ -31,6 +31,7 @@
 #define __ARCH_POWER_ISA_HH__
 
 #include "arch/generic/isa.hh"
+#include "arch/power/miscregs.hh"
 #include "arch/power/registers.hh"
 #include "arch/power/types.hh"
 #include "base/logging.hh"
@@ -49,7 +50,7 @@ class ISA : public BaseISA
 {
   protected:
     RegVal dummy;
-    RegVal miscRegs[NumMiscRegs];
+    RegVal miscRegs[NUM_MISCREGS];
 
   public:
     void clear() {}

src/arch/power/isa/includes.isa

@@ -70,6 +70,7 @@ output exec {{
 #include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
 #include "arch/power/isa_traits.hh"
+#include "arch/power/miscregs.hh"
 #include "arch/power/utility.hh"
 #include "base/condcodes.hh"
 #include "cpu/base.hh"

src/arch/power/registers.hh

@@ -29,10 +29,10 @@
 #ifndef __ARCH_POWER_REGISTERS_HH__
 #define __ARCH_POWER_REGISTERS_HH__
 
+#include <cstdint>
+
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/power/miscregs.hh"
-#include "base/types.hh"
 
 namespace PowerISA
 {
@@ -62,12 +62,6 @@ const int NumFloatArchRegs = 32;
 
 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
 const int NumFloatRegs = NumFloatArchRegs;
-const int NumVecRegs = 1;  // Not applicable to Power
-                           // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to Power
-                               // (1 to prevent warnings)
-const int NumCCRegs = 0;
-const int NumMiscRegs = NUM_MISCREGS;
 
 // Semantically meaningful register indices
 const int ReturnValueReg = 3;

src/arch/power/se_workload.hh

@@ -28,6 +28,7 @@
 #ifndef __ARCH_POWER_SE_WORKLOAD_HH__
 #define __ARCH_POWER_SE_WORKLOAD_HH__
 
+#include "arch/power/miscregs.hh"
 #include "arch/power/registers.hh"
 #include "params/PowerSEWorkload.hh"
 #include "sim/se_workload.hh"

src/arch/power/utility.cc

@@ -45,9 +45,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     for (int i = 0; i < NumFloatRegs; ++i)
         dest->setFloatReg(i, src->readFloatReg(i));
 
-    // Would need to add condition-code regs if implemented
-    assert(NumCCRegs == 0);
-
     // Copy misc. registers
     copyMiscRegs(src, dest);
 

src/arch/riscv/isa.cc

@@ -49,7 +49,7 @@
 namespace RiscvISA
 {
 
-M5_VAR_USED const std::array<const char *, NumMiscRegs> MiscRegNames = {{
+M5_VAR_USED const std::array<const char *, NUM_MISCREGS> MiscRegNames = {{
     [MISCREG_PRV]           = "PRV",
     [MISCREG_ISA]           = "ISA",
     [MISCREG_VENDORID]      = "VENDORID",
@@ -178,7 +178,17 @@ M5_VAR_USED const std::array<const char *, NumMiscRegs> MiscRegNames = {{
 
 ISA::ISA(const Params &p) : BaseISA(p)
 {
-    miscRegFile.resize(NumMiscRegs);
+    _regClasses.insert(_regClasses.begin(), {
+            { NumIntRegs },
+            { NumFloatRegs },
+            { 1 }, // Not applicable to RISCV
+            { 2 }, // Not applicable to RISCV
+            { 1 }, // Not applicable to RISCV
+            { 0 }, // Not applicable to RISCV
+            { NUM_MISCREGS }
+    });
+
+    miscRegFile.resize(NUM_MISCREGS);
     clear();
 }
 
@@ -226,7 +236,7 @@ ISA::hpmCounterEnabled(int misc_reg) const
 RegVal
 ISA::readMiscRegNoEffect(int misc_reg) const
 {
-    if (misc_reg > NumMiscRegs || misc_reg < 0) {
+    if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
         // Illegal CSR
         panic("Illegal CSR index %#x\n", misc_reg);
         return -1;
@@ -314,7 +324,7 @@ ISA::readMiscReg(int misc_reg)
 void
 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
 {
-    if (misc_reg > NumMiscRegs || misc_reg < 0) {
+    if (misc_reg > NUM_MISCREGS || misc_reg < 0) {
         // Illegal CSR
         panic("Illegal CSR index %#x\n", misc_reg);
     }

src/arch/riscv/registers.hh

@@ -111,13 +111,6 @@ const int NumMicroIntRegs = 1;
 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs;
 const int NumFloatRegs = 32;
 
-const unsigned NumVecRegs = 1;  // Not applicable to RISC-V
-                                // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to RISC-V
-                               // (1 to prevent warnings)
-
-const int NumCCRegs = 0;
-
 // Semantically meaningful register indices
 const int ZeroReg = 0;
 const int ReturnAddrReg = 1;
@@ -278,7 +271,6 @@ enum MiscRegIndex {
 
     NUM_MISCREGS
 };
-const int NumMiscRegs = NUM_MISCREGS;
 
 enum CSRIndex {
     CSR_USTATUS = 0x000,

src/arch/sparc/insts/static_inst.cc

@@ -29,6 +29,10 @@
 
 #include "arch/sparc/insts/static_inst.hh"
 
+#include "arch/sparc/miscregs.hh"
+#include "arch/sparc/registers.hh"
+#include "base/bitunion.hh"
+
 namespace SparcISA
 {
 

src/arch/sparc/interrupts.hh

@@ -32,6 +32,7 @@
 #include "arch/generic/interrupts.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/registers.hh"
 #include "cpu/thread_context.hh"
 #include "debug/Interrupt.hh"

src/arch/sparc/isa.cc

@@ -31,6 +31,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/decoder.hh"
 #include "arch/sparc/interrupts.hh"
+#include "arch/sparc/miscregs.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
@@ -61,6 +62,15 @@ static const PSTATE PstateMask = buildPstateMask();
 
 ISA::ISA(const Params &p) : BaseISA(p)
 {
+    _regClasses.insert(_regClasses.end(), {
+            { NumIntRegs },
+            { NumFloatRegs },
+            { 1 }, // Not applicable for SPARC
+            { 2 }, // Not applicable for SPARC
+            { 1 }, // Not applicable for SPARC
+            { 0 }, // Not applicable for SPARC
+            { NumMiscRegs }
+    });
     clear();
 }
 

src/arch/sparc/isa.hh

@@ -33,7 +33,7 @@
 #include <string>
 
 #include "arch/generic/isa.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/reg_class.hh"
 #include "sim/sim_object.hh"

src/arch/sparc/isa/includes.isa

@@ -47,6 +47,7 @@ output header {{
 #include "arch/sparc/insts/unimp.hh"
 #include "arch/sparc/insts/unknown.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/registers.hh"
 #include "base/condcodes.hh"
 #include "base/logging.hh"

src/arch/sparc/process.cc

@@ -31,6 +31,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/handlers.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "base/loader/elf_object.hh"

src/arch/sparc/registers.hh

@@ -31,7 +31,6 @@
 
 #include "arch/generic/vec_pred_reg.hh"
 #include "arch/generic/vec_reg.hh"
-#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/sparc_traits.hh"
 #include "base/types.hh"
 
@@ -94,17 +93,10 @@ const int FramePointerReg = INTREG_I6;
 const int SyscallPseudoReturnReg = INTREG_O1;
 
 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
-const int NumVecRegs = 1;  // Not applicable to SPARC
-                           // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to SPARC
-                               // (1 to prevent warnings)
-const int NumCCRegs = 0;
 
 const int NumFloatRegs = 64;
 const int NumFloatArchRegs = NumFloatRegs;
 
-const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
 } // namespace SparcISA
 
 #endif

src/arch/sparc/remote_gdb.cc

@@ -124,6 +124,7 @@
 #include <csignal>
 #include <string>
 
+#include "arch/sparc/miscregs.hh"
 #include "base/intmath.hh"
 #include "base/remote_gdb.hh"
 #include "base/socket.hh"

src/arch/sparc/tlb.cc

@@ -33,6 +33,7 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/interrupts.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/mmu.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"

src/arch/sparc/utility.cc

@@ -205,9 +205,6 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
         dest->setFloatReg(i, src->readFloatReg(i));
     }
 
-    // Would need to add condition-code regs if implemented
-    assert(NumCCRegs == 0);
-
     // Copy misc. registers
     copyMiscRegs(src, dest);
 

src/arch/sparc/utility.hh

@@ -30,7 +30,7 @@
 #define __ARCH_SPARC_UTILITY_HH__
 
 #include "arch/sparc/isa_traits.hh"
-#include "arch/sparc/registers.hh"
+#include "arch/sparc/miscregs.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/bitfield.hh"
 #include "base/logging.hh"

src/arch/x86/isa.cc

@@ -30,6 +30,10 @@
 
 #include "arch/x86/decoder.hh"
 #include "arch/x86/mmu.hh"
+#include "arch/x86/registers.hh"
+#include "arch/x86/regs/ccr.hh"
+#include "arch/x86/regs/int.hh"
+#include "arch/x86/regs/misc.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "params/X86ISA.hh"
@@ -104,7 +108,7 @@ ISA::clear()
 {
     // Blank everything. 0 might not be an appropriate value for some things,
     // but it is for most.
-    memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
+    memset(regVal, 0, NUM_MISCREGS * sizeof(RegVal));
 
     // If some state should be non-zero after a reset, set those values here.
     regVal[MISCREG_CR0] = 0x0000000060000010ULL;
@@ -134,6 +138,17 @@ ISA::ISA(const X86ISAParams &p) : BaseISA(p), vendorString(p.vendor_string)
 {
     fatal_if(vendorString.size() != 12,
              "CPUID vendor string must be 12 characters\n");
+
+    _regClasses.insert(_regClasses.end(), {
+            { NumIntRegs },
+            { NumFloatRegs },
+            { 1 }, // Not applicable to X86
+            { 2 }, // Not applicable to X86
+            { 1 }, // Not applicable to X86
+            { NUM_CCREGS },
+            { NUM_MISCREGS },
+    });
+
     clear();
 }
 
@@ -409,13 +424,13 @@ ISA::setMiscReg(int miscReg, RegVal val)
 void
 ISA::serialize(CheckpointOut &cp) const
 {
-    SERIALIZE_ARRAY(regVal, NumMiscRegs);
+    SERIALIZE_ARRAY(regVal, NUM_MISCREGS);
 }
 
 void
 ISA::unserialize(CheckpointIn &cp)
 {
-    UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
+    UNSERIALIZE_ARRAY(regVal, NUM_MISCREGS);
     updateHandyM5Reg(regVal[MISCREG_EFER],
                      regVal[MISCREG_CR0],
                      regVal[MISCREG_CS_ATTR],

src/arch/x86/registers.hh

@@ -49,8 +49,6 @@
 namespace X86ISA
 {
 
-const int NumMiscRegs = NUM_MISCREGS;
-
 const int NumIntArchRegs = NUM_INTREGS;
 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs;
 const int NumCCRegs = NUM_CCREGS;
@@ -68,14 +66,9 @@ enum DependenceTags {
     FP_Reg_Base = 128,
     CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
     Misc_Reg_Base = CC_Reg_Base + NumCCRegs,
-    Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
+    Max_Reg_Index = Misc_Reg_Base + NUM_MISCREGS
 };
 
-const int NumVecRegs = 1;  // Not applicable to x86
-                           // (1 to prevent warnings)
-const int NumVecPredRegs = 1;  // Not applicable to x86
-                               // (1 to prevent warnings)
-
 // semantically meaningful register indices
 //There is no such register in X86
 const int ZeroReg = NUM_INTREGS;