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arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined

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In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool
of implementation defined registers, provided that reg numbers
are in the following range:

<op1> is in the range 0 - 7
<CRn> can take the values 11, 15
<CRm> is in the range 0 - 15
<op2> is in the range 0 - 7

Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-05-09 17:56:03 +01:00
parent 97c33d677f
commit 84ba92ed75
1 changed files with 7 additions and 3 deletions
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10
src/arch/arm/miscregs.cc
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@@ -2082,9 +2082,12 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
break;
M5_FALLTHROUGH;
default:
// S3_<op1>_11_<Cm>_<op2>
return MISCREG_IMPDEF_UNIMPL;
}
break;
M5_UNREACHABLE;
case 12:
switch (op1) {
case 0:
@@ -2370,7 +2373,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
}
break;
}
break;
// S3_<op1>_15_<Cm>_<op2>
return MISCREG_IMPDEF_UNIMPL;
}
break;
}