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arch-vega: Add Vega D16 decodings and fix V_SWAP_B32

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Vega adds multiple new D16 instructions which load a byte or short into
the lower or upper 16 bits of a register for packed math. The decoder
table has subDecode tables for FLAT instructions which represents 32
opcodes in each subDecode table. The subDecode table for opcodes 32-63
is missing so it is added here.

The opcode for V_SWAP_B32 is also off by one- In the ISA manual this
instruction is opcode 81, the instruction before is 79, and there is no
opcode 80, so the decoder entry is swapped with the invalid decoding
below it.

Change-Id: I278fea574ea684ccc6302d5b4d0f5dd8813a88ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/71899
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2023-06-28 16:35:54 -05:00
parent 079fc47dc2
commit 841e6fe978
1 changed files with 2 additions and 2 deletions
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4
src/arch/amdgpu/vega/decoder.cc
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@@ -495,7 +495,7 @@ namespace VegaISA
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::subDecode_OP_FLAT,
&Decoder::decode_invalid,
&Decoder::subDecode_OP_FLAT,
&Decoder::subDecode_OP_FLAT,
&Decoder::subDecode_OP_FLAT,
&Decoder::decode_invalid,
@@ -3140,8 +3140,8 @@ namespace VegaISA
&Decoder::decode_OP_VOP1__V_CVT_NORM_I16_F16,
&Decoder::decode_OP_VOP1__V_CVT_NORM_U16_F16,
&Decoder::decode_OP_VOP1__V_SAT_PK_U8_I16,
&Decoder::decode_OP_VOP1__V_SWAP_B32,
&Decoder::decode_invalid,
&Decoder::decode_OP_VOP1__V_SWAP_B32,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,