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gpu-compute: Fix Y-dimension ABI decode

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We currently have a bug in decoding workitem ID from the kernel
descriptor with multiple dimensions.  The enable_vgpr_workitem_id bits
are currently seperated into x and y components, when they should be
treated as a single 2 bit value, where y is enabled when it is > 0,
and z is enabled when it is > 1.  The current setup allows a kernel
launch with vgprs reserved for the z dimension and not the y dimension,
which is incorrect.

Change-Id: Iee64b207feb95bcf064898d5db33b8f201e25323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29965
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
This commit is contained in:
Michael LeBeane
2019-04-23 14:49:31 -04:00
committed by Anthony Gutierrez
parent e4f7982e90
commit 83fe4754e7
2 changed files with 3 additions and 4 deletions
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4
src/gpu-compute/hsa_queue_entry.hh
View File

@@ -417,8 +417,8 @@ class HSAQueueEntry
* workitem Id in the X dimension is always initialized.
*/
initialVgprState.set(WorkitemIdX, true);
initialVgprState.set(WorkitemIdY, akc->enable_vgpr_workitem_id_y);
initialVgprState.set(WorkitemIdZ, akc->enable_vgpr_workitem_id_z);
initialVgprState.set(WorkitemIdY, akc->enable_vgpr_workitem_id > 0);
initialVgprState.set(WorkitemIdZ, akc->enable_vgpr_workitem_id > 1);
}
// name of the kernel associated with the AQL entry

3
src/gpu-compute/kernel_code.hh
View File

@@ -130,8 +130,7 @@ struct AMDKernelCode
uint32_t enable_sgpr_workgroup_id_y : 1;
uint32_t enable_sgpr_workgroup_id_z : 1;
uint32_t enable_sgpr_workgroup_info : 1;
uint32_t enable_vgpr_workitem_id_y : 1;
uint32_t enable_vgpr_workitem_id_z : 1;
uint32_t enable_vgpr_workitem_id : 2;
uint32_t enable_exception_address_watch : 1;
uint32_t enable_exception_memory_violation : 1;
uint32_t granulated_lds_size : 9;