mem-ruby: MOESI_CMP_dir cleanup
Removed unused states and actions Change-Id: I3dc684c78d4b92d219e71522ddb706a13f9874d1 Signed-off-by: Tiago Muck <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18415 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: John Alsop <johnathan.alsop@amd.com> Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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@@ -562,22 +562,6 @@ machine(MachineType:L1Cache, "L1 cache protocol")
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}
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}
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action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") {
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enqueue(responseNetwork_out, ResponseMsg, cacheResponseLatency()) {
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assert(is_valid(cache_entry));
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out_msg.addr := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.SenderMachine := MachineType:L1Cache;
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out_msg.Destination.add(mapAddressToMachine(address,
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MachineType:L2Cache));
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out_msg.DataBlk := cache_entry.DataBlk;
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out_msg.Dirty := cache_entry.Dirty;
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out_msg.Acks := 0; // irrelevant
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
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peek(requestNetwork_in, RequestMsg) {
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assert(is_valid(cache_entry));
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@@ -725,7 +709,7 @@ machine(MachineType:L1Cache, "L1 cache protocol")
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mandatoryQueue_in.dequeue(clockEdge());
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}
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action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
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action(l_popForwardQueue, "l", desc="Pop forwarded request queue.") {
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requestNetwork_in.dequeue(clockEdge());
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}
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@@ -884,15 +868,6 @@ machine(MachineType:L1Cache, "L1 cache protocol")
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}
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}
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action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
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peek(responseToL1Cache_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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assert(cache_entry.DataBlk == in_msg.DataBlk);
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cache_entry.DataBlk := in_msg.DataBlk;
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cache_entry.Dirty := in_msg.Dirty;
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}
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}
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action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
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if (L1Dcache.isTagPresent(address)) {
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L1Dcache.deallocate(address);
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@@ -86,10 +86,7 @@ machine(MachineType:L2Cache, "Token protocol")
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IFGX, AccessPermission:Busy, desc="Blocked, forwarded global GETX to local owner/exclusive. No other on-chip invs needed";
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IFGS, AccessPermission:Busy, desc="Blocked, forwarded global GETS to local owner";
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ISFGS, AccessPermission:Busy, desc="Blocked, forwarded global GETS to local owner, local sharers exist";
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// UNUSED
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IFGXX, AccessPermission:Busy, desc="Blocked, forwarded global GETX to local owner but may need acks from other sharers";
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OFGX, AccessPermission:Busy, desc="Blocked, forwarded global GETX to owner and got data but may need acks";
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OLSF, AccessPermission:Busy, desc="Blocked, got Fwd_GETX with local sharers, waiting for local inv acks";
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// writebacks
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@@ -1546,14 +1543,6 @@ machine(MachineType:L2Cache, "Token protocol")
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unset_cache_entry();
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}
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action(w_assertIncomingDataAndCacheDataMatch, "w", desc="Assert that the incoming data and the data in the cache match") {
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peek(responseNetwork_in, ResponseMsg) {
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assert(is_valid(cache_entry));
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assert(cache_entry.DataBlk == in_msg.DataBlk);
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}
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}
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action(uu_profileMiss, "\um", desc="Profile the demand miss") {
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++L2cache.demand_misses;
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}
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@@ -1585,13 +1574,6 @@ machine(MachineType:L2Cache, "Token protocol")
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L1requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
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}
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action(zz_recycleResponseQueue, "\z\z", desc="Send the head of the mandatory queue to the back of the queue.") {
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peek(responseNetwork_in, ResponseMsg) {
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APPEND_TRANSITION_COMMENT(in_msg.Sender);
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}
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responseNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency));
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}
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action(st_stallAndWaitL1RequestQueue, "st", desc="Stall and wait on the address") {
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stall_and_wait(L1requestNetwork_in, address);
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}
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@@ -1617,19 +1599,19 @@ machine(MachineType:L2Cache, "Token protocol")
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// TRANSITIONS
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//*****************************************************
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transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only, L1_PUTX}) {
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transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_PUTO, L1_PUTS, L1_PUTS_only, L1_PUTX}) {
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st_stallAndWaitL1RequestQueue;
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}
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transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {
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transition({II, IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX, OLSXS, IGS, IGM, IGMLS, IGMO, IGMIO, OGMIO, IGMIOF, OGMIOF, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {L1_GETX, L1_GETS}) {
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st_stallAndWaitL1RequestQueue;
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}
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transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX,OLSXS, IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, L2_Replacement) {
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transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, ILXW, OW, SW, OXW, OLSXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX,OLSXS, IGS, IGM, IGMLS, IGMO, MM, SS, OO, OI, MI, MII, OLSI, ILSI, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, L2_Replacement) {
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zz_recycleL1RequestQueue;
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}
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transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {
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transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX,OLSXS, IGS, IGM, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {Fwd_GETX, Fwd_GETS, Fwd_DMA}) {
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zz_recycleGlobalRequestQueue;
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}
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@@ -1637,7 +1619,7 @@ machine(MachineType:L2Cache, "Token protocol")
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zz_recycleGlobalRequestQueue;
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}
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transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, OFGX, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {Inv}) {
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transition({IFGX, IFGS, ISFGS, IFGXX, IFLXO, ILOW, ILOXW, ILOSW, ILOSXW, SLSW, OLSW, ILSW, IW, OW, SW, OXW, OLSXW, ILXW, IFLS, IFLO, IFLOX, IFLOXX, IFLOSX,OLSXS, MM, SS, OO, SLSS, OLSS, OLSF, IGMIOFS, ILOSD, ILOSXD, ILOD, ILXD, ILOXD}, {Inv}) {
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zz_recycleGlobalRequestQueue;
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}
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@@ -69,7 +69,6 @@ machine(MachineType:Directory, "Directory protocol")
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OO, AccessPermission:Busy, desc="Blocked, was in owned";
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MO, AccessPermission:Busy, desc="Blocked, going to owner or maybe modified";
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MM, AccessPermission:Busy, desc="Blocked, going to modified";
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MM_DMA, AccessPermission:Busy, desc="Blocked, going to I";
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MI, AccessPermission:Busy, desc="Blocked on a writeback";
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MIS, AccessPermission:Busy, desc="Blocked on a writeback, but don't remove from sharers when received";
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