dev-arm: Define a ParentMem object for DTB autogen

A memory willing to autogenerate child nodes can do that directly in
the generateDeviceTree method.  However sometimes portions of memory
(child nodes) are tagged for specific applications. Hardcoding the
child node in the parent memory class is not flexible, so we delegate
this to the application model, which is registering the generator
helper via the ParentMem interface

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I5fa5bac0decf5399dbaa3804569998dc5e6d7bc0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34376
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

src/dev/arm/RealView.py

@@ -543,7 +543,40 @@ class HDLcd(AmbaDmaDevice):
 
         yield node
 
-class MmioSRAM(SimpleMemory):
+class ParentMem(SimpleMemory):
+    """
+    This is a base abstract class for child node generation
+    A memory willing to autogenerate child nodes can do that
+    directly in the generateDeviceTree method.
+    However sometimes portions of memory (child nodes) are tagged
+    for specific applications. Hardcoding the child node in the
+    parent memory class is not flexible, so we delegate this
+    to the application model, which is registering the generator
+    helper via the ParentMem interface.
+    """
+    def __init__(self, *args, **kwargs):
+        super(ParentMem, self).__init__(*args, **kwargs)
+        self._generators = []
+
+    def addSubnodeGenerator(self, gen):
+        """
+        This is the method a client application would use to
+        register a child generator in the memory object.
+        """
+        self._generators.append(gen)
+
+    def generateSubnodes(self, node, state):
+        """
+        This is the method the memory would use to instantiate
+        the child nodes via the previously registered generators.
+        """
+        for subnode_gen in self._generators:
+            node.append(subnode_gen(state))
+
+class MmioSRAM(ParentMem):
+    def __init__(self, *args, **kwargs):
+        super(MmioSRAM, self).__init__(**kwargs)
+
     def generateDeviceTree(self, state):
         node = FdtNode("sram@%x" % long(self.range.start))
         node.appendCompatible(["mmio-sram"])
@@ -559,6 +592,8 @@ class MmioSRAM(SimpleMemory):
             state.addrCells(self.range.start) +
             state.sizeCells(self.range.size()) ))
 
+        self.generateSubnodes(node, state)
+
         yield node
 
 class FVPBasePwrCtrl(BasicPioDevice):